耗尽层

ZrB2+SiC陶瓷高温氧化过程中SiC耗尽层的形成机制研究

Study on the Formation Mechanism of SiC Depletion Layer during High Temperature Oxidation of ZrB_2 + SiC

本文证明了椭圆柱面Schottky结的耗尽层边缘也是一个与结共焦的椭圆柱面。

This paper demonstrates that the edge of the depletion layer of an elliptically cylindrical schottky-junction shows an elliptical cylinder that shares the same focal point with the Schottky-junction .

同时考虑了栅介质、沟道耗尽层和埋层SiO2中的二维效应，结果只与边界条件与长沟解的差有关，具有清晰的物理意义。

It is only related to the difference between the boundary condition and long channel solution , thus has clear physical meaning .

当电路工作时，用于电容设计的MOS管的栅极与衬底之间形成耗尽层，利用串联补偿方法提高电容的线性度。

All capacitors are realized using MOS devices operated in the depletion region , and MOSCAPS are linearized by a series compensation technique .

另一方面，在栅极下面引入的轻掺杂N型缓冲层降低了扩展在导电沟道中的耗尽层，从而提高了输出电流Ids并减小了栅电容Cg。

Meanwhile , a light-doped n-type buffer layer under the gate reduces the depletion in the channel , resulting in an increase in the output current and a reduction in the gate-capacitance .

文章提出了精确描述自对准双扩散MOS器件阈值电压的解析模型，给出了其沟道中杂质的二维分布和源结耗尽层宽度的计算方法；

A threshold voltage analytical model of the self-aligned double-diffused MOS ( SADDMOS ) device is proposed . The channel doping 2D-distribution and the calculation of depletion width of the source junction are presented .

通过对器件体内各物理量的定量分析，得出PN结对肖特基的作用是通过其耗尽层和两PN结之间的间隙来影响肖特基的导电沟道这一结论。

According to the analysis of physical quantities in the body , we got a conclusion that the effect of PN junction on Schottky is through its depletion layer and the gap between two PN junctions .

提出并实验证明了该结构形成的高阻区厚度不是垂直pn结耗尽层的厚度，而是最低层的pn结的深度。

The thickness of high resistance is not equivalent to the width of the depletion region of the vertical pn junctions , but the depth of the bottom pn junction in the substrate are both proposed and validated .

利用扫描电子显微镜（SEM）对电化学刻蚀多孔InP的形貌进行了表征，用耗尽层模型和场强化效应模型讨论了多孔InP刻蚀的机制。

Porous InP is prepared by electrochemical etching , which is characterized using scanning electron microscopy ( SEM ) . The etching mechanism of porous InP is discussed with the model of the depletion layer and the field enhancement effect .

通过测量锐钛矿相纳米TiO2的直流伏安特性，研究了成型压力、烧结及测量条件（在空气和真空中测量）对电导的影响，并用双耗尽层模型对实验结果进行了解释。

The effects of formation pressure , sintering and measurement conditions ( in air or in vacuum ) on electrical conductivity are studied by means of the measurements of DC voltage current characteristic . Experimental results are explained using the double depletion layer model .

提出了DMOS器件的二维阈值电压模型，分析了耗尽层宽度的变化，并得到了模型的数学表达式。

The 2D threshold voltage model of DMOS devices is proposed . Depletion width is analyzed and the expression of the 2D threshold voltage model of DMOS devices is given .

研究了PSD光敏面各层厚度和SiO2薄膜厚度对PSD波长响应灵敏度的影响，认为p层的厚度主要影响PSD在短波段的响应度，而耗尽层对PSD的中长波响应有着很大的影响；

The effect of every layer thickness and SiO_2 thickness on the spectral response is analysed and calculated . The spectral response of PSD is affected by the thickness of p layer mainly at short wavelength and by the thickness of the depletion layer mainly at long wavelength .

根据Gupta和Carlson提出的ZnO压敏电阻的缺陷势垒模型，提出了修正的缺陷势垒模型用来解释氧化镨晶界势垒的形成，在耗尽层内存在VO和VO。

Based on the defect barrier model for ZnO based varistors proposed by Gupta and Carlson , a modified defect barrier model was introduced to explain the formation of the grain boundary barriers , (?) and (?) as the donor defect exist in the depletion layer .

在耗尽层内电场最强处，电子温度达到4000K；在强电场下，电子温度将严重偏离晶格温度，形成所谓热电子。

In the region of high electric field , the electron temperature is much higher than the lattice temperature , and the so-called hot electrons appear . At the position of the highest electric field within the depletion layer , the electron temperature can reach 4 000 K.

电场辅助阳极连接碱金属耗尽层模型

Model for alkali depletion-layer growth during electric field assisted anodic bonding

深耗尽层电荷耦合掐他们一周内耗尽了资金。

Deep depletion ccd They exhausted the funds in a week .

也导出了两方法的耗尽层宽度公式。

A formula of depletion layer width is also deduced .

高反压器件终端结构模拟中耗尽层的先验估计

Prior-Estimation of Depletion Region in Modeling Termination Structure of High Reverse Voltage Devices

硅耗尽层少子产生率的强电场效应

Effect of High Electric Field on Minority Carrier Generation in Silicon Depletion Layer

另外，硅窗口将耗尽层引入衬底，因而提高了器件的击穿电压。

Hence the breakdown voltage is enhanced .

对质子射程同耗尽层厚度相当时的质子能谱进行的理论计算与实验现象一致。

With the depletion layer thicknesses , the calculated spectra are consistent with experimental phenomena .

耗尽层的时域介电谱

Time Domain Dielectric spectra of depletion Layer

给出了耗尽层宽度与偏压之间的关系。

The expressions are also given for the voltage dependence of the depletion layer width .

三探针测试硅外延片中雪崩击穿时耗尽层宽度的面接触模型

The Area Contact Model of Depletion Layer Width Under Avalanche Breakdown in Si Epitaxial Wafer by a Three-Probe Method

耗尽层-晶圆片上的电场区域，此区域排除载流子。

Depletion Layer - A region on a wafer that contains an electrical field that sweeps out charge carriers .

界面电位降与测量电容、薄膜电容及耗尽层电容有关。

The voltage drop of interface is relevant to the measured capacitance , the film capacitance and the depletion capacitance .

利用泊松方程（零偏压时耗尽层宽度作为边界条件）积分计算出其电场分布、电势分布等重要结特性。

Some important characteristics , such as build-in electric field distribution , build-in potential distribution were calculated by poisson ′ equation .

结合耗尽层宽度确定了产生微等离子体噪声的局部区域大小。

Combining the duty ratio and the wide of the depletion layer , the volume of microplasma noise local region has been confirmed .

数值模拟结果表明，器件栅极电压越负，肖特基结的耗尽层越厚，源漏电流越小；

The results show that while the gate biases are more negative , the Schottky depletion layer is thicker and the source-drain current flow is lower .

对于长沟道器件来说，源-衬结及漏-衬结沿沟道的耗尽层可以在沟道中忽略。

For a long-channel device , the junction depletion layers along the channel due to the source-substrate and drain-substrate junctions constitute a negligible portion of the channel .