组合逻辑

现场可编程门阵列（FPGA）包含有大量实现组合逻辑的资源，可以完成较大规模的组合逻辑电路设计，提高系统的集成化。

FPGA includes such great number of resources for realizing combinatorial logic to complete large-scale combinatorial circuit designing .

采用这种模型，SPICE程序就可以直接分析组合逻辑电路，甚至模糊逻辑电路。

They make it possible for SPICE to analyze combinatorial logic circuits directly , even fuzzy logic circuits .

用Java实现组合逻辑电路仿真平台

Using Java to Realize the Combinational Logic Circuit Simulation Platform

基于异或门的组合逻辑化简CAD

Function Minimization of Combinational Logic Cad Based on XOR Gate The Door

基于MATLAB的数字组合逻辑电路建模与仿真

Digital Combined Logic Circuit Modeling And Simulation Based On MATLAB

综合多输出组合逻辑二级电路CAD软件算法的改进二、末日意识

An improvement algorithm of CAD software of multiple output combinational logic two stage circuit

组合逻辑故障检测R系数法

The detection of faults of combinational networks using a method of coefficients " r "

K式结构大规模组合逻辑集成电路

Large-scale Combinational Logic IC of K-type Architecture

FPGA设计中的组合逻辑与时钟方案

Combinational Logic and Clocking Schemes in FPGA Design

组合逻辑电路的Petri网仿真分析

Simulation of Combinational Logic Circuits Based on Petri Net

利用协议组合逻辑（ProtocolCompositionLogic，PCL）证明了方案的认证性和秘密性，并对方案中的所有权转换协议进行了仿真分析。

The authentication and secrecy of the scheme is proved by Protocol Composition Logic ( PCL ) .

CMOS组合逻辑电路的功耗分析研究

Research on power analysis of CMOS combinational logic circuits

利用协议组合逻辑（ProtocolCompositionLogic，PCL）对提出的协议进行了形式化安全性证明。

The formal security proof of PMAP is given by using the protocol composition logic ( PCL ) .

讨论了通过FPGA对PWM波进行组合逻辑变换的设计方法。

Comments are made to designing method of combined logical switch to PWM wave with FPGA .

介绍了使用中规模集成电路数据选择器的原理以及使用它实现逻辑函数的方法。针对具有n位地址的数据选择器，使用降维卡诺图的思想实现了任何输入变量数大于n+1的组合逻辑函数。

The present paper introduces the principle of utilizing middle-scale integrated circuit data selector and how to realize logic functions by using it .

N（23,12）是一个异步的组合逻辑电路，能用12个大数逻辑门和77个异或门电路来实现。

N ( 23,12 ) is an asynchronous combinational logic circuit which can be implemented with 12 majestic-logic gates and 77 exclusive-OR gates .

基于CPLD组合逻辑电路的VHDL实现

Implementation of Combinatorial Logical Circuit Based on CPLD in VHDL

算法通过了对20变量以下的组合逻辑函数标准的Benchmark例题和部分组合逻辑函数典型实例验证，保证了优化结果正确性和有效性。

The algorithm is a doable-effective method by some examples and Standard Benchmark 's sample proved .

VHDL高级综合系统中组合逻辑综合的研究与实现

Research and Realization of Combinational Logic Synthesis in VHDL High-Level Synthesis System

用SPICE程序对组合逻辑电路的仿真

The Simulation of Combination Logical Circuits With the SPICE Program

应用PSpice分析组合逻辑电路中的竞争冒险

Analysis of Competition and Adventure in Assembled - Logic Circuits Using PSpice Simulation

利用MSI实现组合逻辑电路的设计方法

A Design with Mid-scale Integrated Circuit to Realize Combined Logical Circuit

结论用MSI数据选择器可实现任意组合逻辑函数。

Conclusion Using MSI data selector can implement any combined logic functions .

任意BCD码的B/BCD组合逻辑变换网络

A Combinational Logic B / BCD Conversion for any BCD Code

本文提出了适于SPICE程序仿真、拓扑不变的组合逻辑电路模型。

This paper presents some new models of combinatorial logic circuits , which are tope-invariant and suitable to SPICE .

系统设计结合了电力机车的具体运行环境和通用PLC的特点，将整个组合逻辑固化成软件，来实现其基本控制功能。

Combining the working environment of Electric locomotive and the characteristics of the in general Programmable Logic Controller , the system design will become the software for whole control logical function .

Searle（西尔）复合函数及两级组合逻辑网络设计

Searle Complex Functions and Design of Two-class Logical Networks

用MUX实现组合逻辑的卡诺图列解法

The Method of Karnaugh Diagram of Using MUX for Realizing Composite Logic

提出了一种基于时序等价性检查技术的组合逻辑单元系统级可靠性分析理论和方法，并基于VIS系统下用C语言实现了原型工具。

A sequential equivalence checking based approach for system level soft error reliability evaluations proposed . It 's prototype tool is accomplished in C language on the VIS system .

用数据选择器（MUX）可进行任意组合逻辑的设计。

We can realize any design of combinatorial logic by demultiplexer ( MUX ) .