片总线

为了实现IP与SOC中片上总线的快速、有效连接，可以采用为IP设计总线封装的方法。

Bus wrapper can realize the effective interfacing between the IP and on chip bus in the SOC .

SoC架构下片上总线的研究与设计

The Design and Implementation of On-Chip Bus in SoC

三种SoC片上总线的分析与比较

The Analysis and Comparison of three SoC On-chip Buses

基于Wishbone片上总线的PCIbridge核的研究和应用

Research and Application of the PCI Bridge IP Core Based on the Wishbone OCB

SoC片上总线技术的研究

Research of SoC on chip bus

SOC设计通常采用层次化片上总线体系结构，不同的IP集成在不同类型的总线上。

The design of SOC usually adopts hierarchical on-chip-bus architecture , different IPs are integrated on different types of buses .

SOPC设计中的两种片上总线分析

Analysis of Two on - Chip Buses for SOPC Design

在SOC设计中，片内总线作为SOC集成的互连结构，可以把各个功能模块互连起来，使知识产权核（IPCore）的移植、设计、复用变得容易。

In SOC design , On-chip Bus can connect functional modules together , and facilitate the design of Intellectual Property ( IP ) Core .

SoC设计中WISHBONE片上总线的设计与开发

Development and Application of WISHBONE Technology in SoC Designing

在SoC设计中，片内总线可以把各个模块互连起来，使知识产权（Intellectualproperty，IP）核的设计、移植和复用更加容易。

In the SoC design , on-chip interconnect bus can connect functional modules together and make the Intellectual Property ( IP ) core design , migration and reuse easier .

IP模块和片上总线，以及EDA工具接口的标准化，是解决IP模块标准化的很好途径；

An efficient and feasible method to solve these problems is developing standards for IP block interface , on chip bus and the interface between various EDA tools .

从而方便设计师对这两种片上总线的充分理解，并为SOPC及其他SoC设计中的总线选择提供参考。

Thus , let designers fully appreciate the two on-chip buses , and provide them with reference for SOPC and other SoC design .

该算法不改变现有总线结构，仍可复用连接在总线上的IP，以最小的代价有效地降低了片上总线上所消耗的功耗。

This solution does not change the bus architecture , and maintain the reusability of IP on bus . The result shows , it reduces the power consumption on bus effectively with minor cost .

Avalon片上总线协议的形式化建模与模型检验分析

Formal Modeling and Model Checking Analysis of the Avalon System-on-Chip Bus Protocol

Wishbone作为一种免费开放的SoC片上总线接口标准，当前有着十分广泛的应用。

Wishbone is a free and open interface standard of OCB for SoC , and is very popular in current application .

可重用片上总线Wishbone的研究

Research on Reuse On-chip Bus Wishbone

针对这一挑战，阐述在ARM指令集模拟器基础上扩展片上总线（AMBA）模型、SDRAM控制器模型和SDRAM模型。

Faced with it , the AMBA bus model , SDRAM controller model and SDRAM model based on ARM ISS simulator are designed .

Wishbone总线是一种高性能的片上总线，它结构简单，灵活，硬件开销小。

Wishbone is a high performance on chip bus with its simple structure , flexible and low cost .

根据不同领域的验证对象和不同层次的验证模块，功能验证有很多研究方向，如针对CPU、片上总线、存储器等的验证。

According to verified objects in different areas and verified modules in different levels , there are many function verification directions , such as CPU , on-chip bus , memory and so on .

在充分了解现有IP核的基础上，设计相应的满足片上总线标准的主设备和从设备接口，并根据需要实现片上总线标准中的各种类型的传输，包括突发传送等。

On the base of the existing IP cores , the relevant master interfaces and slave interfaces according with those on-chip bus standards are designed , and the transfer types of the on-chip bus standards by the needs are realized .

针对现有片上总线结构，为降低SoC总线功耗，避开现有总线编码技术在应用上的局限，本文提出了两种低翻转率的SoC总线编码算法。

To lower power dissipation of SoC bus and to keep away from the limitation of existing bus encoding technology in application field , two algorithms based on encoding are proposed for the existing bus specification .

IP（Intellectualproperty）核技术的采用极大提高了SoC（Systemonchip）的开发效率，而片上总线（On-ChipBus）的选择和IP核封装是实现IP核与芯片连接的关键步骤。

The adoption of IP ( Intellectual Property ) technology has improved the efficiency of SoC ( System on Chip ) designing greatly . The choosing of OCB ( On-chip Bus ) and wrapping of IP are crucial steps in connecting IPs with chip .

而AMBA总线最早由ARM公司在1996年提出，是广泛应用于32位嵌入式微处理器中的片上总线，现在已经是事实上的工业标准。

The AMBA was introduced by ARM Ltd in 1996 and now it is widely used as the OCB in SoC designs . The AMBA protocols are the de-facto standard for 32-bit embedded processors .

随着集成电路设计进入到系统芯片（SoC）时代，板极系统的总线互连结构也发展成为系统芯片的层次化总线体系一片上总线。

Integrated circuit design has entered into the era of System on Chip ( SoC ), the bus interconnect architecture of System on Board have also developed into a kind of hierarchy architecture-On Chip Bus ( OCB ) .

在市场现有的各种片内总线中，由ARM公司开发的高级微处理器总线架构（AMBA）市场占有率最高，成为一种最流行的工业标准片内总线结构。

In all kinds of On-chip Buses available in the market , Advanced Microcontroller Bus Architecture ( AMBA ) which is designed and standardized by ARM company is one of the most popular industrial standards .

而基于片上总线的SoC在设计上遇到了全局时钟难以同步、地址空间有限、无法支持多节点并行通讯以及系统扩展不够灵活等问题，严重制约了系统性能的提高。

But the chip bus based SoC design encounters many problems , such as hard to synchronize the global clock , address space is limited , cannot support multi-node paralle communications , as well as the system expansion is not flexible enough .

研究AMBAASB和AMBAAHB片上总线标准，对其中的各种传输类型的时序进行详细的分析。

The major work and productions are summarized as below : AMBA ASB and AMBA AHB standards are studied , and all kinds of transfer types are analyzed .

讨论了PCI主桥的应用和Wishbone片上总线技术，详细介绍了基于Wishbone总线的PCIbridge核的功能、内部结构和操作方式。

In this paper , the application of Host / PCI bridge and the technology of Wishbone OCB are discussed . The functionality , architecture and operation of the PCI bridge IP core based on the Wishbone OCB are intro ˉ duced in detail .

本论文为采用标准片上总线实现片上系统积累了一定的经验，并建立了ASB和AHB两种总线系统模型，以便于以后在系统功能扩展时加入新的模块。

This dissertation has contributed to designing SoC using standard on-chip buses , and realized the bus system of ASB and AHB , which is convenient for adding new cores in function development .

PCI9054局部端总线与AHB片上总线具有较大的差异，分组密码协处理器能不经修改的应用到这两种总线环境中，证明了其设计具有较高的可重用性。

The application of the block cipher coprocessor in both PCI9054 local bus system and AHB bus system with no modification well proved the reusability of the coprocessor design .