时序电路

卫星信息处理系统中基于FPGA的时序电路设计

A Design of Sequential Circuit base on FPGA in the Signal Processing System of Satellite

Pspice在脉冲异步时序电路分析中的应用

The Application of PSPICE for Pulse Nonsynchronous Sequential Circuit Analysis

CCD时序电路与数据缓存器的一体化设计

An integrative design of multi-channel CCD timing generator and data cache

基于触发器次态函数K图的同步时序电路设计

Design of Synchronous Sequential Circuits Based on the K-map of Next State Functions of Flip-flops

用遗传算法实现CMOS时序电路最大功耗估计

Maximum Power Estimation for CMOS Sequential Circuits by Genetic Algorithm

在此基础上，利用Uk门阵列实现三值时序电路。

Based on it , ternary sequential circuits are implemented by using array of universal-logic-module Uks .

基于VHDL描述的时序电路测试方法探析

Analysis for Sequential Circuits Testing Generation Based on VHDL Description

基本数字时序电路Spice宏模型的建立

Building the Basic Digital Sequence Circuit Macro-Model in Spice

基于FPGA的TDI-CCD时序电路的设计

The design of timing generation of TDI-CCD based on FPGA

利用CPLD复杂可编程逻辑器件，结合VHDL硬件描述语言，设计了一种线阵CCD驱动时序电路。

Use CPLD and VHDL together to design the time sequence driving circuit for a kind of linear CCD .

基于GAL的焊接电源时序电路设计

The Logic Design of Sequence Circuit of Welding Supply Based on GAL

基于CPLD和VHDL的一种线阵CCD驱动时序电路的设计与实现

Design and realization of the time sequence driving circuit for a kind of linear CCD based on CPLD and VHDL

采用二元判定图（BDD）作为工具来描述时序电路是非常有意义和有效的。

It is very effective that use BDD to describe the synchronous circuits .

在分析星载FPGA内时序电路特性以及FPGA可编程资源特性的基础上，指出了FPGA内同步时序电路出现时钟偏斜现象的机理。

Mechanism about the clock skew of synchronism sequential circuit has been presented , based on analyzing the characteristics of programmable resources and sequential circuit in FPGA .

BESⅢ漂移室电子学的校准时序电路

Calibration timing circuit of BES ⅲ MDC electronics

双阶跃JK触发器和多阶跃时序电路

Double Jump JK Flip-Flop and Multiple Jump Sequential Circuits

一种基于EPROM的时序电路设计方法及应用

A Method of Sequential Circuit Design on the Basis of EPROM and Use

应用MSI移位寄存器设计时序电路的新方法

Sequential Circuit Design Using MSI Shift Register

针对同步时序电路VHDL设计的有效模型判别器VERIS

VERIS : An Efficient Model Checker for Synchronous VHDL Designs

基于BDD的时序电路等价性验证

Sequential Equivalence Checking Based on BDD

介绍了一个针对同步时序电路VHDL设计的性质验证的解决方案&一个有效的符号模型判别器VERIS。

A solution for property verification of synchronous VHDL design is introduced , and VERIS an efficient symbolic model checker is implemented .

用于光纤光栅传感解调系统的线阵InGaAs驱动时序电路的设计

Design on Driving Generator for Linear InGaAs Used in Fiber Grating Sensors Demodulation System photoelectrically balanced slidewire potentiometer

并且本文还讨论了基于MSI计数器时序电路的分析和设计方法。

The methods to analyse and design sequencial logic circuit in medium scale integrated circuit counter are discussed .

系统的时序电路采用Veriloghdl语言进行编写，实现对CMOS图像传感器的调控目的。

System timing circuits using Verilog HDL language to write , to achieve the purpose of the regulation of CMOS image sensors . 3 .

通过等效电路分析、考虑参数选取和整体时序电路的实现，提出具有信息恢复能力的静态绝热CMOS记忆电路。

An adiabatic static CMOS memory circuit to have ability in information recovery by means of analyzing equivalent circuit , choosing parameter and realizing complete function of sequential circuit is presented .

介绍了用EPROM进行时序电路设计的原理、方法和应用实例。

The article gives the principle , method and applied example of the EPROM used as sequential circuit design .

异步时序电路分析的一种OBDD方法

An OBDD Method for Analysis of Asynchronous Sequential Circuits

应用绝热JK触发器，并以十进制加法计数器为例演示了能量恢复型时序电路的设计。

A decade counter was used to illustrate the design of energy recovery sequential circuit using the proposed JK flip-flops .

本课题以FPGA（EP2C8Q208C8N）为主控芯片，利用FPGA内部的逻辑资源在FPGA内部生成NIOS软核处理器、一些数字组合电路和时序电路。

In the system , FPGA is the controller chip , using internal logic resources inside the FPGA to generate the NIOS soft-core processor , Some digital integrated circuits and sequential circuits .

接着我们设计了三值ECL组合电路、时序电路和部分四值ECL电路。

We designed ternary combined circuits , sequential circuits and some quadruple circuits based on the structure of symmetric inputs and outputs .