信号处理机

AD电路是雷达信号处理机的关键组成电路。

AD circuit is the key circuit of radar signal processor .

一种基于DSP和FPGA的雷达信号处理机设计

Design of a Radar Signal Processor Based on DSP and FPGA

基于DSP的神经网络信号处理机的研究

Study of Neurocomputer Based on DSP for Signal Processing

可扩展机载SAR信号处理机的研究

Research of Scalable Processor for On - Board Airborne SAR

SAR成像信号处理机的接口与通信设计

Design of Interface and Communication for SAR Imaging Signal Processor

大规模阵列信号处理机的FPGA设计

The FPGA Design of Large Scale Array Signal Processor

基于星上实时信号处理机的Chirpscaling算法实现方法

Implementation of Chirp Scaling algorithm based on space-borne real-time SAR processor

基于多DSP技术的SSR实时信号处理机

Real-Time SSR Signal Processing System Based on Multi-DSP

位片式高速FFT信号处理机设计

A Design of High-speed FFT Signal Processor

信号处理机的高速ADC模块动态性能在线测试

High-Speed ADC of Signal Processor Dynamic Performance Testing

主要介绍基于DSP与CPLD的雷达/雷达干扰实验系统信号处理机的设计与研制。

The paper introduced the design and development of signal processor of radar / radar-jamming experiment system based on DSP and CPLD .

可编程序信号处理机高级SCSI可编程接口

Programmable signal processor ASPI Advanced SCSI Programming Interface

舰载跟踪雷达MTD信号处理机海杂波的抑制

Suppression of Sea Clutter for MTD Signal Processor of Shipborne Tracking Radar

本文的工作是在研究几种滤波算法的基础上提出了一种改进的自适应卡尔曼滤波，并采用DSP和FPGA等器件实现了某雷达信号处理机的数据处理部分。

This paper proposes an improved adaptive Kalman filter based on researching on these filter theories and using DSP and FPGA implement a radar data processing system .

本文对脉冲多普勒雷达信号处理机中的CFAR检测器进行了仿真研究。

This paper studies and simulates the CFAR detection in pulse Doppler radar processor .

可编程DBS信号处理机的设计

The design of programable DBS signal processor

然后在某研究所暗室条件下，对具有DBF功能的雷达信号处理机天线各方向接收信号的能量图进行了实测。

Under certain darkroom conditions , DBF function of radar signal processor is tested .

一个可用于发射脉冲宽度为1μs的MTD信号处理机

A MTD Signal Processor Adaptable to a Transmited Pulse width of 1 μ s

论文从理论和工程实践两个方面对SAR实时信号处理机及实时存储系统的研究、开发做了有益的探讨。

From the theory and project two aspects , this paper do some valued discussion on the study of SAR real time processor and real time data storage system .

最后，结合某具体雷达信号处理机，用FPGA实现雷达信号处理、高速链路口通信和系统控制。

Finally , based on the development of specific radar signal processor , the implementation of radar signal processing , high-speed link-port communication and system control are implemented by FPGA .

介绍一种新研制的以自适应MTI技术为核心的雷达数字信号处理机。

A new developed adaptive radar signal processor based on adaptive MTI technique is introduced .

在信号处理机硬件设计中，采用多DSP并行处理技术实现高速运算，并通过自定义总线和链路口实现数据传输，使得板卡具有很高的运算能力和数据传输能力。

In the hardware design , multi-DSP parallel processing technique is used to realize high speed operation , and multi-bus architecture and multi-level interconnection is adopted to perform data transmission among the modules .

实时信号处理机的实验表明，本文方法能实时和有效的实现机载SAR运动补偿，获得满意的成像质量。

The experiment results of the real-time signal processor show that this method can effectively compen - sate the airplane motion error in real-time , and improve the SAR image quality .

该文详细论述了基于FPGA的单板信号处理机的模块化设计及实现，并通过仿真和测试验证了设计的正确性。

This paper discusses the modularized design and implementation of single board signal processor based on FPGA in detail , and the validity of the design is verified by simulation and test .

最后结合一些实测数据对该雷达信号处理机的信号处理板的杂波抑制性能进行分析，并且与Matlab中的仿真结果进行了比对，论证了该处理板设计中杂波抑制的可行性。

Finally combining with the practical data analyzing , the comparison with the results that from Matlab , this paper arrives the conclusion that the Clutter Compression of the Radar Signal Processor is feasible .

本文讨论机载前视雷达中可编程多普勒波束锐化（DBS）信号处理机的结构和实现方法。

This paper discussed structure and realized method of a programmable Doppler Beam Sharpening signal processor for Front-Looking airborne radar .

给出了编码二相调制准连续波雷达信号处理机的硬件设计框图，并对A/D转换模块、FPGA模块、双口RAM模块及电源和时钟模块进行了电路设计。

The hardware frame of QCW radar signal processor is offered . the circuit of ADC module , FPGA module , dual-port RAM module and power and clock module is presented .

硬件电路设计与实现：完成了信号处理机母板硬件电路的设计，绘制了原理图并制作了PCB。

Hardware circuit design and implementation : The mother-board hardware circuit of processor was designed . The schematic diagram was drawn , and the PCB was produced . 3 .

本文从任务规划、数据传输模式和处理单元的拓扑结构等三方面对可扩展实时并行SAR信号处理机进行了分析研究，提出一种可扩展实时并行SAR信号处理机方案。

This paper discusses the scalable real time parallel SAR processor from task planning , data transmitting mode and topology structure of computation unit , and proposes a scheme of real time parallel SAR processor .

用于21单元H-S波前传感器的自适应光学波前信号处理机

Adaptive Optics Wavefront Signal Processor for 21 Unit H S Wavefront Sensor