逻辑单元

您还可以针对数据逻辑单元数量（datalogicalunitnumbers，LUNs）调优StorageAreaNetwork（SAN）存储子系统，而不会影响rootvg。

You can also tune the Storage Area Network ( SAN ) storage subsystem just for the data logical unit numbers ( LUNs ) without affecting rootvg .

物理磁盘的表示，比如逻辑单元编号（LUN）

Representations of physical disks , such as logical unit numbers ( LUNs )

针对一种多模式逻辑单元结构FPGA的工艺映射

Technology Mapping for FPGA with Multi-mode Logic Cell

通用的FPGA逻辑单元映射工具

A Universal Logic Cell Mapping Tool for FPGA

一种FPGA新型逻辑单元结构的设计

A Design of FPGA Programmable Logic Cell Structure

本文首先讨论了3D几何图形加速引擎中的基本运算单元和基本逻辑单元。

First , the basic computing units and logic units of the 3D accelerating graphics engine are talked over .

每一个LU（逻辑单元）都具有一个根结点元素，亦即最顶部的包。

Each LU has a root element , which is the top-most Package .

而且选用的FPGA内部还具有锁相环的逻辑单元，为本次设计带来了很大的方便。

And the choice has PLL internal FPGA logic modules for this design brings great convenience .

基于FPGA的算术逻辑单元设计

Design of ALU Based on FPGA

换句话说，在当前的Rational用户界面中，逻辑单元不能够被可视化的排列为逻辑层次。

In other words , in the current Rational user interface , LUs cannot be visually arranged into arbitrary logical containment hierarchies .

也就是说，您之所以能够清楚的看到ProjectExplorer中反映的逻辑单元，是因为他们总是出现在顶层条目中。

That is , you see LUs clearly reflected in the Project Explorer because they always appear as top-level items .

在讨论所涉及的产品中，您能够创建多个逻辑单元（作为UML模型）。

In the products under discussion , you can create multiple LUs ( as UML Models ) .

基于BIST的FPGA逻辑单元测试方法

An approach for testing FPGA logic cells based on BIST

第五章分析了DSP的架构，并对算术逻辑单元和乘/累加器进行了验证与综合，然后在乘/累加器性能比较的基础上证明了本方案中DSP的优越性。

Chapter 4 analyzed the architecture of the master processor and did the verification and synthesis work to its sub module .

该工具充分利用新型FPGA逻辑单元的层次化特征，减少实现电路所需的逻辑单元的个数。

The packing tool uses the hierarchical characteristic of the new FPGA logic structure to reduce the number of CLBs .

结合实际电路中各输出具有输入共享的特点，提出了一种新型逻辑单元结构及其装箱（packing）工具。

A new FPGA logic structure and CLB packing tool are investigated based on the input-sharing features of real circuits .

激活两个逻辑单元（LU）之间会话的请求。参见BIND。

A request to activate a session between two logical units ( LUs ) . See BIND .

GaAsIC逻辑单元与或非DCFL特性计算机示波器方式模拟及电路设计

Simulation of Characteristics for GaAs IC DCFL Gate and Circuit Design

换而言之，业务逻辑单元（假设C或Java等编程语言）不需要使用特定于表示的方式生成数据。

In other words , business logic units ( presumably in some programming language like C or Java ) don 't have to generate data in a presentation-specific manner .

可以将流量IP地址组织为称为流量IP地址组（TIP组）的逻辑单元，由ZeusTrafficManager集群托管这些逻辑单元。

Organized into logical units called traffic IP address groups ( TIP group ), traffic IP addresses are hosted by clusters of Zeus Traffic Managers .

模型/逻辑单元作为分割的顶层容器出现在ProjectExplorer之中，并且不能够（在此时）被嵌套在其他的逻辑容纳结构中。

Model / LUs appear as separate top-level containers in the Project Explorer and cannot ( at this time ) be nested within other logical containment structures .

每一项的前三个数字分别指SCSI总线、设备标识和LUN（逻辑单元号，LogicalUnitNumber）。

The first three numbers for each item refer to SCSI bus , device ID , and LUN ( Logical Unit Number ), respectively .

物理卷也可能是通过VirtualI/OServer表示的SAN逻辑单元号（LUNs）或文件备份设备。

The physical volumes may be SAN logical unit numbers ( LUNs ) or file-backed devices presented via the Virtual I / O Server .

因此，如果需要分别转化多个Java项目，最好是为每个项目都建立一个单独的模型/逻辑单元。

Thus , if there is a need to transform multiple Java projects individually , it may work best to establish a separate model / LU for each one .

SOA是一种在计算环境中设计、开发、部署和管理离散逻辑单元（服务）的模型。

Service-oriented architecture ( SOA ) is a model used to design , develop , deploy and manage discrete logic units ( services ) in computing environment .

本文主要研究高性能FPGA可编程逻辑单元中分布式RAM和移位寄存器两种时序功能的设计实现方法。

This paper presented the design and implementation of two sequential circuits in FPGA configurable logic block , namely , distributed RAM and shift register .

SCSI目标通常为启动程序提供一个或多个逻辑单元号（LUN）。

The target usually provides the initiators one or more logical unit numbers ( LUN ) .

一支拥有共享代码词汇表的团队的工作区有可能仅仅包括一个在其自己的Eclipse项目中的核心功能模型/逻辑单元。

The workspace of a team that owns the shared coded vocabularies might contain only a Core Capabilities model / LU within its own Eclipse project .

在计算机存储介质上，LUN仅是分配给逻辑单元的号码。

In computer storage , a LUN is simply the number assigned to a logical unit .

在FPGA电路平台上，只需要约4·2K的逻辑单元，因此它是一种可以通过低成本集成电路实现的快速分数位平面编码技术。

And it needs merely 4.2K logic cells in FPGA device so it can be implemented with low cost integrated circuit .