时序逻辑电路

基于Matlab的时序逻辑电路的实验教学探索

Experiment Teaching Exploration of Sequential Logic Circuit Based on Matlab

时序逻辑电路的Petri网分析方法

Analysis of sequential logic circuit based on Petri net

《时序逻辑电路》CAI课件的设计及实现

Design and realization of CAI courseware for clock and logic circuit

利用PLA设计时序逻辑电路

A Design for Combinational Logic Circuit Using PLA

应用DT触发器的时序逻辑电路的设计方法

Design Method of Sequential Logic Circuits Using DT Flip - Flops

用EPROM简化时序逻辑电路的设计

Simplifying the Design of Sequential Logical Circuit with Eprom

一个分析时序逻辑电路ICAI系统的设计与实现

An Icai System for Analyzing Sequential Logic Circuits

给出了APD信号放大电路和控制时序逻辑电路原理图。

The thesis offers APD signal amplify circuit chart and controlling time-series logic circuit principle chart bearing practical applied value .

CMOS敏感器不是I2C总线电路，因此同ARM连接必须有驱动电路（时序逻辑电路）。

When it connects to ARM , driving circuits ( sequential logical circuits ) is necessary because CMOS star sensor doesn 't belong to I2C bus circuits .

本文论述用ROM的存贮阵列构成新颖的组合逻辑电路和时序逻辑电路的基本原理，并给出两个实际的阵列式逻辑电路的设计方法。

This paper review elementary theory for new logic circuit with ROM memory array , and provide design method for two practical array logic circuit .

其中，总线接口，A/D采样控制，双端口RAM缓存，控制译码，时序逻辑电路均由CPLD实现。

In this instrument , bus interface , controlling of sampling of A / D , double port RAM , controlling coding , timing logic circuit are all realized by CPLD .

该软件能够模拟组合逻辑电路、同步和异步时序逻辑电路及部分GAL等可编程逻辑元件组成的电路。

The software is capable of simulating circuits combined with combinational circuits , synchronous and asynchronous sequential logic circuits , and some programmable logic devices .

依据教学设计理论，从教学目标、教学策略、导航策略和界面设计4个方面，阐述了《时序逻辑电路》CAI课件的设计思想；

According to the theory of instructional design , this essay elaborates the design thoughts of CAI courseware for clock and logic circuit in brief four sides ; Instructional objectives , Instructional tactics , Tactics of navigation and design of interface .

在光通信数字接收机中，为了达到系统的位同步，结合数字锁相环的基本原理，采用现场可编程技术，设计了位同步信号的时序逻辑电路，并用FPGA芯片实现了整个位同步电路。

In order to achieve bit synchronization in the optical communication digital receiving circuit , combined with fundamental of digital PLL , timing logical circuit of bit synchronization circuit is designed , and the whole circuit is programmed in FPGA chip via field programmable technology .

导出了DT触发器的激励表，提出了应用DT触发器的时序逻辑电路的设计方法，并给出了设计实例。

In this paper , DT flip - flop excitation table is developed , the design method of sequential logic circuits using DT flip - flop is presented , and the design example using the method is given .

这类门电路可以用于构成四值组合逻辑电路和时序逻辑电路，也可以和DYL系列电路配合使用。

This kind of gate circuit can be used in forming 4 value combination logic circuit and order part logic circuit , it also can be combined with DYL series circuits .

分析了APD光电接收系统的噪声问题，并对APD激光信号接收系统电路、前置放大电路、控制时序逻辑电路、DC/DC变换电路进行了设计，采取了APD偏压模糊控制。

The thesis analyses the problems on the noise of APD photoelectric receiving system . Author designs APD laser signal receiving system circuits , front amplify circuit , controlling time-series logic circuits , DC / DC transform circuits . And takes APD bias voltage fuzzy control .

逻辑线路的设计是比较复杂的，对于初学者来说是一大难点，用EPROM可以简化逻辑设计，本文在文〔1〕的基础上给出简化时序逻辑电路设计的方法。

Logical circuit design is very complicated , so it is difficult for begin-ners . Logic design can be simplified with Eprom . This paper , based on essay ~ ( [ 1 ] ), gives the way of simplifying the sequential logical circuit .

在时序逻辑电路的设计中，利用电路所存在的冗余态来参与状态分配，更符合“A-H规则”，从而获得较简单的电路结构，并且消除了无效状态和所谓的自校正问题。

In the design of the sequential logic circuit , redundant state is used to assign the state , so the assignment is more consistent to the A-H rule , and simple sequential structure can be obtained .

2~2值时序逻辑电路的研究及应用

Study and Application of 2 ~ n Valued Sequential Logical Circuit

提出了一种同步时序逻辑电路设计的新方法&次态方程联立法。

And it is fit for all synchronous sequential logic circuits design .

四值逻辑的化简及时序逻辑电路设计

The simplification and the design of sequential logic circuit to four-valued logic

一类时序逻辑电路的逻辑参数提取激励波形自动生成

Automatic Waveform Generation Technique for Special Sequential Circuit in Logic Parameter Extraction

基于时钟设计的异步时序逻辑电路设计法

Design of Asynchronous Sequential Logic Circuit Based on Design of Clock Signal

同步型时序逻辑电路的机助设计

A Computer Aided Design Program Of Sequential Logic Circuit

同步时序逻辑电路设计方法的研究

A study on designing of synchronous sequential logic circuits

异步时序逻辑电路的最小时钟覆盖设计法

A clock coverlay method to design asynchronous logic circuit

同步和异步时序逻辑电路统一分析的新方法

A New Method for Unitized Analysis of Synchronous and Asynchronous Sequential Logic Circuits

异步时序逻辑电路设计的一种简明方法

Simple Method to Design A synchronous Sequential Logic Circuit

时序逻辑电路的次态卡诺图综合设计法

Next-State Karnaugh Map comprehensive design of sequencial logic circuit