组合逻辑电路

用Java实现组合逻辑电路仿真平台

Using Java to Realize the Combinational Logic Circuit Simulation Platform

N（23,12）是一个异步的组合逻辑电路，能用12个大数逻辑门和77个异或门电路来实现。

N ( 23,12 ) is an asynchronous combinational logic circuit which can be implemented with 12 majestic-logic gates and 77 exclusive-OR gates .

基于MATLAB的数字组合逻辑电路建模与仿真

Digital Combined Logic Circuit Modeling And Simulation Based On MATLAB

组合逻辑电路的Petri网仿真分析

Simulation of Combinational Logic Circuits Based on Petri Net

CMOS组合逻辑电路的功耗分析研究

Research on power analysis of CMOS combinational logic circuits

基于CPLD组合逻辑电路的VHDL实现

Implementation of Combinatorial Logical Circuit Based on CPLD in VHDL

用SPICE程序对组合逻辑电路的仿真

The Simulation of Combination Logical Circuits With the SPICE Program

应用PSpice分析组合逻辑电路中的竞争冒险

Analysis of Competition and Adventure in Assembled - Logic Circuits Using PSpice Simulation

利用MSI实现组合逻辑电路的设计方法

A Design with Mid-scale Integrated Circuit to Realize Combined Logical Circuit

采用这种模型，SPICE程序就可以直接分析组合逻辑电路，甚至模糊逻辑电路。

They make it possible for SPICE to analyze combinatorial logic circuits directly , even fuzzy logic circuits .

本文提出了适于SPICE程序仿真、拓扑不变的组合逻辑电路模型。

This paper presents some new models of combinatorial logic circuits , which are tope-invariant and suitable to SPICE .

介绍了以Java2标准中的Applet技术开发组合逻辑电路网络仿真实验平台的原理。

The realization of a combinational logic circuit simulation platform with Applet technology of Java 2 is introduced in this paper .

用提出的定理，可以求出组合逻辑电路的单故障全测试集，其结果和布尔差分法与SPOOF法相同。

By this approach , the single fault of combined logical circuit can be detected .

方法针对设备存在的问题，在原系统电路中增加逻辑控制功能及抗干扰措施，设计出组合逻辑电路，采用CMOS数字集成电路实现其功能。

Methods Aim at equipment 's problem , design and add a new CMOS digital circuit on the original circuit to add logic control function and improve the ability of anti-jamming .

本文论述用ROM的存贮阵列构成新颖的组合逻辑电路和时序逻辑电路的基本原理，并给出两个实际的阵列式逻辑电路的设计方法。

This paper review elementary theory for new logic circuit with ROM memory array , and provide design method for two practical array logic circuit .

介绍了GAL器件用作组合逻辑电路设计的一般方法及应该注意的一些问题。

The general method of using GAL for the design of digital circuits has been introduced and some related problems have been called for attention .

该软件能够模拟组合逻辑电路、同步和异步时序逻辑电路及部分GAL等可编程逻辑元件组成的电路。

The software is capable of simulating circuits combined with combinational circuits , synchronous and asynchronous sequential logic circuits , and some programmable logic devices .

在以CMOS为开关器件的数字集成电路芯片的设计中，由于或非门优于与非门，故应该使用所介绍的方法，直接采用或非门设计组合逻辑电路芯片。

Because the NOR gate is superior than the NAND gate . the method introduced in this paper should be adopted and the NOR gate ought to be directly used when designing digital integrated circuit with CMOS as switches .

本文叙述了用MSI（主要是数据选择器和译码器）设计组合逻辑电路的方法，并分几种情况加以讨论。

The paper related on the design with MSI ( especially with data selector and decoder ) to realize combined logical circuit and had a discussion on several cases .

由于结合了确定性测试和伪随机测试的优点，该方法具有低功耗、长度短、故障覆盖率高、测试图形自动生成等特色，特别适于CMOS组合逻辑电路的测试。

The BIST has merits of combining deterministic and pseudorandom test , and has the features of low power consumption , low length , high fault coverage , and pattern generated automatically , and is especially suitable for testing of CMOS combinational logic circuits .

能完成对任意基于CDL语言描述的组合逻辑电路或布尔函数，实现其BDD表示并通过对BDD的操作实现对相应组合电路或布尔函数的操作。

It can give BDD presentation of Boolean function or arbitrary combination logic circuits which are presented by CDL , and can realize different operation of Boolean function by the operation to BDD .

这类门电路可以用于构成四值组合逻辑电路和时序逻辑电路，也可以和DYL系列电路配合使用。

This kind of gate circuit can be used in forming 4 value combination logic circuit and order part logic circuit , it also can be combined with DYL series circuits .

本文介绍了基于CPLD组合逻辑电路的VHDL设计思想，并结合嵌入式教学系统的译码和I/O控制电路的具体应用，做了较为详细的例证，其中包含部分代码。

The paper presents the implementation idea of combinatorial logical circuit based on CPLD in VHDL , and offers a specific application named decoding and I / O control of embedded teaching system to explain how to carry out the idea , including part of programming code .

为避免这种现象，给出了Haar函数归一化的一种方法以及在变量数<6时用ha系数图判断组合逻辑电路险象的方法，该方法具有简单、直观的特点。

To avoid this circumstance , this paper puts forward a method for normalizing Haar function and judging dangerous appearance in combination logic circuit by use of ha coefficient map under the condition of variable number < 6 . This method has the characteristics of being simple and direct .

公用技术组合逻辑电路设计方法的初步探讨

Discuss the way of communal technique to design combinational logic circuits

多输出组合逻辑电路的简化设计

The Simplified Design of Combinatorial Logical Circuit with Many Output Variables

组合逻辑电路的无反变量输入设计

On the Design about Un-inversion Variable Input of Combinational Logic Cricuit

组合逻辑电路的软错误率自动分析平台

An Automated Soft Error Rate Analysis Platform for Combinational Logic Circuits

组合逻辑电路的逆向分析和条件通路法

Backward Analysis and Conditional Path Method for Combinational Logic Circuits

运用数据选择器实现组合逻辑电路设计方法

Design of Combination of Logical Electric Circuit by Data Selectors