闩锁效应

这种器件无寄生闩锁效应，并在较高阳极电压下展现出电流下降而不是饱和或上升的特性。

This device is parasitic latch up free , and exhibits the characteristic of output current decrease , instead of current saturation or increase at higher anode voltage .

高温CMOS集成电路闩锁效应分析

The Analysis of Latch Up Characteristics in High Temperature CMOS Integrated Circuits

CMOS闩锁效应模型分析及计算机模拟

Analysis and Computer Simulation of a CMOS Latch-up Model

CMOS集成电路闩锁效应的形成机理和对抗措施研究

Study on the mechanism of Latch-up effect in CMOS IC and its countermeasures

CMOS电路中的闩锁效应研究

Research on CMOS Latchup

在工艺上，SiGe器件可以采用BiCMOS技术，很好地实现了与CMOS技术的兼容。体硅CMOS的闩锁效应和无闩锁的埋阱CMOS技术

In addition , the Bi CMOS process of SiGe device is compatible with CMOS process of Si device . CMOS Latch-up and Buried well Technology

在高速串行接口的匹配、寄生参数、噪声、闩锁效应、ESD保护等方面，进行版图细致优化，以实现数据传输的高性能和高可靠性。

We work more on detailed layout optimization on matching , parasitic , noise , latch , and ESD protection to reach high performance and high reliability of data transmission .

绝缘体上硅器件（SOI）具有结电容小、抗辐射性能好、优良的亚阈区特性、消除了闩锁效应、适于低压低功耗工作等优点，而被称为二十一世纪的硅集成电路技术。

Silicon-on-insulator ( SOI ) device has the advantages of small junction capacitance , good resisting-radiation property , superior subthreshold characteristics , eliminating the latchup effects , suitable to low-voltage low-power operation , etc.

接着对最新出现的系统级ESD防护进行了系统分析，根据系统级ESD失效机理，提出了软硬件协同设计的解决方案并有效地解决系统级ESD失效引起的闩锁效应。

Secondly , the latest system-level ESD protection were analyzed , According to system-level ESD failure mechanism , a hardware and software co-design solution is proposed , which can effectively solve the system-level ESD failures due to latch-up effect .

重掺杂直拉硅单晶既可以消除CMOS器件的闩锁效应，也能够有效地降低器件的功耗，而广泛用作硅外延片的衬底材料。

The heavily doped Czochralski ( Cz ) silicon could not only eliminate the " latch-up " effect of small feature size CMOS devices , but also effectively reduces the energy loss , therefore is extensively applied as a substrate material of epitaxial silicon wafers .

分析了两种过流保护方法的功能及优缺点，研究并提出了一种可应用于集成稳压器中改善闩锁效应的foldback过流保护电路。

Based on the analysis of two protection methods , an over-current protection circuit which can improve the integrated regulators ' latch-up effect is proposed .

外太空辐射环境主要以三种方式影响CMOS器件：总剂量辐射效应（TID），单粒子翻转效应（SEU）和单粒子闩锁效应（SEL）。

The radiation environment of outer space is capable of effecting CMOS devices in three ways . The first , termed total does , is accumulated ionizing radiation effects . Two other effects are transient phenomenon called Single Event Upset ( SEU ) and Single Event Latchup ( SEL ) .

一种可改善稳压器闩锁效应的过流保护电路

Over-Current Protection Circuit for Improving Regulators ' Latch-up Effect

论文最后介绍了闩锁效应产生的原理，和闩锁效应的触发方式，并且分别从工艺和版图设计方面研究了防止闩锁产生的方法。

At last the paper introduced the principle of latch-up effect , and introduced the method of preventing the latch up separately from the technology and layout design .