运算器

利用FPGA技术，能方便灵活地设计出浮点运算器。

Using FPGA technology may design a floating point calculator conveniently and quickly .

但是由于Java智能卡本身的空间和运算器的限制，传统的一些优化算法并不适用。

Some of the traditional optimization algorithm does not apply to Java Card for its space and calculator restrictions .

基于FPGA的信号互相关运算器研究

Research of signal correlation process based on FPGA

最后设计出了基于FPGA的基本数论变换的实现并基于此实现了快速卷积运算器。

Finally this FPGA-based NTT is designed , and using this design achieve fast convolution .

这个IP模型主要由运算器模块，控制器模块，时钟模块和端口模块四个部分组成。

The IP core is made up of four modules , which are alu_module , control_ module , timer_module and port_module .

CPU的基础部件由运算器，控制器和寄存器三局部组成。

The components of CPU include three typical parts : arithmetic unit , control unit and registers .

利用MFC编写一个简单的四则运算器。

Using MFC to write a simple arithmetic device .

通过时域和频域的数字信号处理的方法，用FPGA器件构成卷积器或FFT运算器，还原出与雷达信号形式相关的杂波信号。

And it is resumed to clutter signal specified to the environment using time domain and spectrum domain algorithm which is FFT calculator or convolator based on FPGA device .

利用数理统计原理，本文分析了任意相位和线性相位结构的复FIR滤波运算器字长的计算方法。

Using the principle of Mathematical Statistics , this paper analyses the method to calculate the word length of complex FIR filtering operators in the arbitrary phase and linear phase strutures .

本论文创新地设计了一种基于流水线结构的多个浮点运算器并行计算的IP硬件体系结构，在有限的硬件资源上实现了速度和面积的最优。

This dissertation newly designs a hardware-based architecture for IPs . The architecture based on pipeline structure , has multiple floating point calculators computing at the same time . Speed and area are balanced in the limited hardware resources .

基于基为4的Montgomery模乘算法和改进的流水线组织结构，文章提出了一种结构优化的可扩展模乘运算器结构。

This paper presents an optimized architecture of a scalable radix-4 modular multiplier , based on radix-4 Montgomery multiplication algorithm and improved pipeline architecture .

本文通过现场可编程门阵列（FPGA）实现FFT的蝶形运算器，有效地提高了运算速度，充分发挥了DSP和FPGA各自的优点。

This paper realizes the butterfly shape arithmetic unit of FFT through the Field Programmable Gate Array ( FPGA ), having improved the speed of operation effectively . That exploits the respective advantages of DSP and FPGA sufficiently .

运算器：运算器是数据加工处理部件，它是由算术逻辑单元（ALU）、累加器、数据缓冲器等组成。

Arithmetic unit : Arithmetic unit is a data processing unit that consists of arithmetic logic unit ( ALU ), accumulator , data buffer , ect .

这个高效率的运算器在本论文中称之为QM-Solver。

This efficient solver in this thesis is called QM-solver .

对于雷达脉冲信号参数的实时性测量问题，由于DSP处理速度的限制，文中采用FPGA硬件实现。在FPGA内部直接实现比较器，运算器等模块，大大简化了测量系统，系统的灵活性也得到增强。

Limited by the processing speed in DSP , radar pulse parameters measurement in real time is implemented in FPGA hardware , with the modules such as comparator and computing device implemented in FPGA directly . This scheme simplifies the measurement system greatly and enhances the flexibility .

在DFT处理器中除WFTA运算器外，还有一个辅助的相移网络和一个供同时处理两个60路超群信号的分离（或组合）单元。

In addition to the WFTA processor , an auxiliary phase shifting network and a signal separator ( or combiner ) for two 60-channel supergroups are included in the DFT processor .

阵列乘法器是在PENTIUM等高速计算机中采用的一种高速乘法运算器，据此讨论其补码阵列乘法器的设计和运算规则。

Array multiplier is one of the high_speed multipliers used in the high_speed computers , such as PENTIUM . This paper discusses the design and operation rules of the complement array multiplier .

在D/S板的设计中，采用EPROM作为正余弦函数运算器，降低了软件开销，缩短了转换时间，大大降低了成本。

In design of the D / S conversion board , EPROM is used to act as sine and cosine function generator in order that the spending of software is deduced and the conversion time is shortened , and the cost is greatly reduced .

立即存取存储器；立即访问存储器；零存储时间存储器在运算器中的寄存器一般为立即存取寄存器。

The register inside APU is generally a zero access register .

图像复合代数运算器的设计与应用

Design & Applications of the Image Complex Algebraic Operation Calculator

剩余数制在加法运算器设计中的应用

Surplus notational system in addition logic unit design application

计算机组成原理的一个浮点数运算器。

Computer principle of a floating point arithmetic unit .

可重组多功能大数运算器的小规模硬件实现

Small-scale hardware implementation of reconfigurable multifunctional large number calculators

80位嵌入式超越函数运算器的设计

Design of an 80-Bit Embedded Transcendental Function Calculator

74181运算器进位延迟时间的测试

Test of the time of delay of carrying on the 181 Arithmetic Logit Unit

本论文的研究就是以角度复用的体全息存储器作为相关运算器，来做图象的相关识别。

This paper is aiming at image recognition based on angle-multiplexed volume holographic correlator .

加减法运算器，袖珍型，靠记录针控制

Adding and subtracting device , pocket-type , operated with a stylus register-to-register arithmetic operation

计算机模拟运算器软件的设计

Design of Computer Software of Simulation Arithmetic Device

一种简单、经济的数字化百分率运算器

A simple and economic digital percentage calculator

而一个倍周期分叉混沌发生器和异或运算器使得加密快速而安全。

A double cycle furcation chaos machine and operation implement make it work fleetly and safely .