恢复电路

时钟恢复电路要从抖动的数据中恢复出时钟，需要找到最佳的采样时刻。

The function of CDR is to extract the clock from the jittering data , which needs to find out the optimum sampling point .

时钟恢复电路的动态特性包括输入抖动容忍范围、输出抖动和锁定速度，这些性能与环路特性密切相关。

The dynamic characteristics of CDR include input jitter tolerance , jitter output and lock-in speed , which are strongly related to the loop characteristics .

基于FPGA的高速时钟数据恢复电路的实现

Design of high-speed clock and data recovery circuit Based on FPGA

10Gb/sCMOS时钟和数据恢复电路的设计

A 10 Gb / s CMOS Clock and Data Recovery Circuit

基于半速率锁相环的5Gb/sCMOS单片时钟恢复电路

5Gb / s CMOS Monolithic Clock Recovery Circuit Rased on Half-rate Phase-locked Loop

一个面积和功耗优化且适用于10/100Base-T以太网的CMOS时钟恢复电路

Power and Area Efficient CMOS Clock Recovery Circuit for 10 / 100 Base-T Ethernet

DVD写时钟恢复电路系统的设计与仿真

System Design and Simulation of Write Clock Recovery for DVD Data

可变速率QPSKModem中码元定时恢复电路的研制

Development of Symbol Timing Recovery Circuit for Variable Rate QPSK Modem

高速时钟恢复电路的ASIC研究与设计

Research and Design of High Speed Clock Recovery Circuit on ASIC

PDP能量恢复电路硬开关问题的研究

Analysis on Hard Switching Problem in Energy Recovery Circuit for Plasma Display Panel

文章实现了用于UHF频段的射频识别（RFID）标签的时钟恢复电路和反向散射调制信号产生电路。

The clock regenerator and backscatter modulator for Ultra High Frequency ( UHF ) RFID application are implemented .

本文研究了锁相环实现的高速CMOS时钟恢复电路的低噪声设计问题。

Low noise , high speed CMOS clock / data recovery ( CDR ) circuit design is treated in this thesis .

设计并实现了部分响应均衡器、定时恢复电路以及Viterbi最大似然序列检测器。

The modules of equalizer , timing recovery and Viterbi detector are implemented .

时钟恢复电路（CRC）从主放大器输出数据信号中提取出时钟信号供数据判决和后续电路使用。

Clock recovery circuit is used to extract clock from the output signal of main amplifier .

这种电路即称为时钟数据恢复电路（CDR）。

This system is called clock and data recovery ( CDR ) .

DVB-C接收机中的时钟恢复电路设计

Design of Timing Recovery Loop for DVB - C Receiver

基于0.18μMCMOS工艺的2.5GB/s时钟恢复电路设计

Design of 2.5 GB / s Clock Recovery Circuit Based on 0.18 μ m CMOS Technique

一种适用于NRZ数据的时钟数据恢复电路

A Clock and Data Recovery Circuit for Non-Return-Zero Data

54Mb/sNRZ时钟数据恢复电路的设计与实现

Design and implementation of a 54Mb / s NRZ clock data recovery circuit

锁相环（Phase-LockedLoop，PLL）因具备独特的倍频和锁相功能而广泛应用于频率综合器、时钟恢复电路等集成电路中。

Phase-Locked Loop ( PLL ) has been widely used in frequency synthesizer and clock data recovery circuit worked as the aim of multiplying frequency and phase-lock .

论文提出一种DVB-C基带芯片中全数字时钟恢复电路的解决方案。

This paper presents an all digital timing recovery loop in a single chip for DVB-C receiver .

高速锁相环（Phase-LockedLoop，PLL）电路作为时钟恢复电路和频率合成器的重要组成部分广泛应用于现代光纤通信和无线通信中，具有非常重要的应用价值。

High speed phase-locked loop circuits as an important component of clock recovery circuit and frequency synthesizer circuit are widely used in modem optical fiber communication and wireless communication .

更高速率系统的研制目前也在开展中。时钟恢复电路（CRC）是光纤通信和许多类似数字通信领域中不可缺少的关键电路。

Clock recovery circuit ( CRC ) is the key component in the optical transmission systems as well as in the field of digital transmission .

根据已有的研究成果，对高速宽带时钟恢复电路进行拓展研究，提出了一种双支路无切换结构的时钟恢复电路，电路采用0.18μMCMOS标准数字工艺设计，目前正在流片的过程中。

Based on the above research , further research for high-speed broadband CDR , a dual-branch structure CDR is proposed , it is designed in 0.18 μ m CMOS process and now in fabrication .

AC-PDP新型能量恢复电路的研究

Novel Energy-recovery Driving Circuit for AC-PDP

根据表面放电AC-PDP的特性及驱动原理，提出了一种两级的能量恢复电路，并对电路工作过程进行了详细的分析。

A new energy recovery driving circuit with two-level voltage wave-shaping characteristics for AC PDP is proposed .

本论文给出了时钟恢复电路的基本原理以及采用PLL型时钟恢复电路的完整的电路设计、模拟结果和版图设计，以及将时钟恢复电路集成到光接收机后的测试结果。

The thesis presents basic principle of CRC and rounded circuit design , simulation results , layout design and testing results of a PLL type CRC , which is incorporated in a optic-fiber receiver chip .

设计实现了2M数据码速调整和恢复电路，并利用数据平滑技术解决了塞入抖动问题。

In this paper we design and realize the circuit of 2M positive justification / recovery , and we solve the problem of stuffing jitter by means of utilizing digital smoothing method .

文中提出了一种以锁相环为基础的622MB/sNRZ码的时钟数据恢复电路。

A 622MB / s Clock data Recovery Circuit for NRZ code , which is based on phase locked loop , is proposed in this paper .

尤其适用于基于锁相环的高速时钟和数据恢复电路（CDR）、高速频率合成器等对速度和抖动性能有很高要求的电路。

The PFD is adapted to the circuits having strict demand in jitter performance , such as high speed clock and data recovery , frequency synthesizer and so on .