千兆网卡

使用硬件描述语言Veriloghdl进行FPGA逻辑设计，包括千兆网卡控制器的实现、UDP/IP协议栈的硬件实现。

We use Verilog HDL on FPGA logic design , including the implementation of network card controller , UDP / IP stack hardware implementation .

文章研究了TCP／IP卸载引擎技术及其原理，并针对数据路径卸载的TOE千兆网卡设计实现了一个支持协议卸载的TCP／IP协议栈。

This paper studies the principle of TCP / IP offload engine ( TOE ), and proposes a design and implementation of TCP / IP stack supporting protocol offload for a TOE Gigabit-NIC .

基于TCP/IP卸载引擎的千兆网卡

Gigabit-NIC Based on TCP / IP Offload Engine

它有一个10千兆以太网卡用于成员与CF之间的高速低延迟通信。

It has a10 gigabit Ethernet card for high-speed , low-latency communication between members and CFs .

本课题基于江苏省重点立项项目千兆加密网卡，完成了对1024位RSA密码算法的研究与实现。

This thesis is based on the Jiangsu province project of " kilomega encrypted network card " . Research and implementation of RSA Cryptography algorithm has been proposed .

千兆以太网卡芯片数模转换电路的设计与实现

Design and implementation of DAC circuit for gigabit ethernet chips

传输消息长度为1196bytes时带宽高达1.18E+08bytes/s，是千兆以太网卡硬件带宽的94.4%。

It provides 1.18E + 08 bytes / s of bandwidth which is 94.4 % of hardware-level bandwidth for 1 196 bytes message .

在考虑服务器和高性能工作站向千兆位/秒升级时，用户必须谨慎地选择千兆位以太网卡。

In considering gigabit-per-second upgrades for servers and power workstations , users must select Gigabit Ethernet NICs carefully .