分频频率

基于FPGA的小数分频频率合成器设计

Design of fractional frequency dividing frequency synthesizer based on FPGA

介绍了一种3V0.35μMBiCMOS工艺实现的1.6GHz小数分频频率合成器。

A 1.6 GHz Σ - Δ fractional-n frequency synthesizer is presented , which is implemented in 3-V 0.35 - μ m BiCMOS process .

分析了无线通信分数分频频率合成器的关键模块∑Δ调制器（sdm）的设计方法，并提出了一种系数能用移位产生的简单高效的单环3阶3位量化sdm结构。

This paper analyzes the design methodology of ΣΔ modulator ( SDM ) used in fractional-N frequency synthesizer for wireless communication , and an efficient and uncomplicated single loop 3rd order 3-bit SDM is proposed .

小数分频频率合成器专用集成电路的研制

The Study of Frequency Synthesizer Decimal Fraction Discerption Frequency Circuits

小数分频频率合成器的研究和实现

The Study and Implementation of Fractional - N Frequency Synthesizer

小数分频频率合成器及其相位补偿技术

Fractional - N Frequency Synthesizer and Its Phase Compensation

分数分频频率合成器的分数杂散抑制方法

Fractional Spur Reduction Techniques in Fractional-N Frequency Synthesizer

小数分频频率合成器的计算机辅助设计

Computer-Aided Design of Fractional-N PLL Frequency Synthesizer

小数分频频率合成器中Δ-∑调制器的量化噪声

An Analysis on Quantization Noise of Δ - Σ Modulator for the Fractional-N Frequency Synthesizer

一种高分辨率∑△小数分频频率合成器

A High Resolution Sigma-Delta Fractional-N Frequency Synthesizer

一种快速换频的小数分频频率合成器

A fast changing-frequence fractional frequence synthesizer

一种适用于任意波形合成系统的两级分频频率合成设计方案

A design method of frequency synthesis applying two grades frequency division technique for arbitrary waveform synthesizer system

高频谱纯度的小数分频频率合成器

A high-purity fractional-N frequency synthesizer

本文介绍了高阶单比特∑△调制器在小数分频频率综合器中的应用。

In this paper , a fractional-N frequency synthesizer based on high-order single-bit Σ△ modulator is introduced .

综合结果表明，该设计能够接收高速差分信号，并能稳定工作在输入时钟的分频频率下。

The result shows that the designed architecture can receive high-speed differential signals and work at the divided frequency stably .

以往对小数分频频率合成器中的Δ-∑调制器的量化噪声大都建立在线性分析的基础上，这样得出的量化噪声近似为高斯噪声。

All analysis of quantization noise for single-loop Δ - Σ modulator for the fractional-N frequency synthesizer is based on linearization assumptions .

本文分析了小数分频频率合成器中存在的相位杂散的问题，以及解决问题的Δ∑调制技术。

The phase noise in fractional-N synthesizer is analysed , and the ΔΣ modulation technology which can eliminate phase noise is introduced .

本论文围绕△∑分数分频频率综合器的设计展开，主要包括鉴频鉴相器、电荷泵、分频器以及i/q分频器等电路模块的设计。

This thesis takes efforts on the design of a △□ fractional frequency synthesizer , including phase detector , charge pump , divider and I / Q divider blocks .

本文介绍了锁相环和频率合成技术的基础理论，并对分数分频频率合成器及其实现技术进行了探讨。

In this paper the basic theory of phase locked loop ( PLL ) and frequency synthesizer technology were introduced , the theory and implement of fraction-N phase locked loop ( FNPLL ) frequency synthesizer were introduced too .

相对于传统的整数分频频率综合器，小数分频频率综合器打破了频率精度对环路带宽的限制，可以使用较高的输入参考频率，这使得频率综合器许多方面的性能都得到了明显的提高。

Compared with conventional integer-N frequency synthesizers , fractional-N frequency synthesizers break the limitation of frequency resolution on loop bandwidth and can use higher input reference frequency . This has improved performance of frequency synthesizers in many aspects significantly .

介绍分频锁相频率合成技术。

The technology of frequency division phase-locked frequency synthesis is introduced .

微机可控小数分频锁相环频率合成器的研制

The development of decimal sub-frequency phase-locked loop frequency synthesizer controlled with microcomputer

仿真结果验证了新型的多模式分频器自动频率控制及拓展线性区间的鉴频鉴相器与电荷泵结构。

Simulation results validate the new MMFD , the AFC algorithm and linear range extended PFD and CP configuration .

最后，对分数分频与整数频率合成器进行了理论上的分析和比较，并通过实验得到了验证。

At last , the difference between FNPLL and NPLL frequency synthesizer 's performance is discussed and analyzed theoretically , and it is testified in the experiment .

小数分频器作为频率综合器的重要组成部分，对频率综合器的输出精度、相位噪声、锁定时间及参考杂散等性能有重要影响。

As a critical part of the frequency synthesizer , the fractional divider seriously affects the output frequency accuracy , phase noise , locking time and reference spur .

提出了一种适用于分数分频锁相环频率综合器的全数字噪声整型Δ∑调制器电路结构新的设计方法，并将其最终实现。

This paper presents the design considerations and implementation of a novel topology digital multi-stage-noise-shaping ( MASH ) delta-sigma modulator suitable for fractional-N phase-locked-loop ( PLL ) frequency synthesis .

首先从频率综合器系统层面分析小数分频器对频率综合器输出精度、相位噪声、锁定时间等性能的影响。

First , the influence of the fractional-N divider on the frequency accuracy , phase noise and locking time of a frequency synthesizer is analyzed on the system level .

本文针对晶体振荡器的温漂特性，参考微处理器温度补偿晶体振荡器原理，根据实时时钟的电路特点，设计了一种基于分频链的频率校准算法。

For this temperature drift character , this paper referred to crystal oscillator temperature compensation principle , according to the feature of RTC circuit , designed a calibration algorithm based on divide-chain frequency .

在数字电视调谐器等多标准应用中，可以用分频器扩展频率综合器的频率范围，同时产生正交信号。

In multi-standard applications , such as the DTV-Tuner , divider may be used to extend the frequency range of the frequency synthesizer , or to generate the quadrature ( I / Q ) signal .

我们可以从16位和32位的累加器所能分频的最高频率可以看出来，同样的器件由于计算的位数的加宽，必然会带来相应的延时。

We can be what can be allotted frequency from 16 places and 32-bit accumulator carriage most high frequency can find out , digit expanded , necessity may bring about corresponding time lapse since the same component secretly scheming against .