寄生电容

提出了用以描述分布式的寄生电容和由于工艺梯度变化而产生的寄生参数不匹配以及STACK内连线的不匹配的模型。

Novel techniques are proposed for modeling the distributed parasitic capacitance , parasitic parameter mismatch due to process gradient and the inner stack routing mismatch .

本文介绍了一种经济实用的利用GIS母线寄生电容串联电抗器谐振升压的原理及实现。

This paper introduces an inexpensive and applied resonance boosting method by using GIS bus line parasitic capacitance and reactor connected in series , and also its principle and realization .

复杂3D寄生电容器的虚拟多介质切割

Virtual-Cutting Method for Parasitic Capacitors with Complex 3D Structures

寄生电容非灵敏有源开关电容网络的一种CAD算法

A Kind of CAD Computing Method of Parasitic-Insensitive Active Switched Capacitor Networks

一个N阶滤波器只需要N个运放，且无寄生电容影响。

A Nth order filter only requires N amplifiers and is insensitive to the parasitic capacitors .

利用GIS母线寄生电容串联电抗器的谐振升压法

The Resonance Boosting Method by Using GIS Bus Line Parasitic Capacitance and Reactor Connected in Series

寄生电容对零电压过渡PWM电路影响及对策

The effect on the zero voltage transition PWM converter caused by parasitic capacitance and its elimination method

VLSI互连寄生电容准三维多极加速提取

A Virtual 3 D Multipole Accelerated Extractor for VLSI Parasitic Interconnect Capacitance

漏栅寄生电容对IGBT工作特性影响的研究

Influence of Body Drain-Gate Capacitor on the Behavior of IGBT

VLSI三维寄生电容提取的层次式h-自适应计算

Hierarchical h-Adaptive Computation in VLSI 3-D Capacitance Extraction

在PCB设计过程中通过对过孔的寄生电容和寄生电感分析，总结出高速PCB过孔设计中的一些注意事项。

Summarise some points for attention of PCB via design through analysis of parasite capacity and inductance .

电流角的大小直接决定了换流过程中MOSFET寄生电容充放电所需电荷的供给量。

The size of the current angle directly determines the charging and discharging precess of MOSFET parasitic capacitor during commutation .

在3DVLSI互连寄生电容的边界元素法计算中，多孔平面的边界元划分是十分困难的问题。

In the computations of3D VLSI parasitic interconnect capacitance , it is very difficult to partition the boundary elements on a multi hole surface .

利用空气桥工艺制作RTD，降低了RTD的寄生电容；

The RTD was fabricated by using air bridge technology , then the autoeciousnesscapacitance is reduced .

SOI指的是在IC的制造过程中采用硅+绝缘层+硅的硅基体结构方式，这种结构方式的优势是可以减小器件的寄生电容并改善器件的性能。

SOI refers to the use of a layered silicon-insulator-silicon substrate in IC manufacturing , which is said to reduce parasitic device capacitance and improve performance .

同时提出了将ESD的寄生电容吸收到LNA输入匹配网络中的设计方式，并与传统的计算方式做了对比。

The LNA design method which absorbs the parasitic capacitance of ESD is introduced and compared with the traditional design method .

本文研究了集成电路多层连线的寄生电容模型、互连线RC树模型的延时估算等电路模拟技术，同时提出了今后该领域的研究方向。

This paper analyses the parasitic capacitance 's pattern of multi-layer cabling and delay estimation of cabling 's RC tree , and puts forward research orientations in this domain .

文章的第四章介绍了通孔的机械特性以及通孔的寄生电容和寄生电感，并用准静态法对via结构的过剩电感进行了计算。

The mechanical property , the parasitical capacitance and the parasitical inductance of the via structure were introduced in the fourth chapter , and the excess inductance of the via structure was computed by using quasi-electrostatic method .

但在测试GIS母线电压互感器时，由于GIS母线存在的寄生电容在额定电压下将附加大量的容性负载，因此不允许使用试品升压。

But the parasitic capacitance existed in GIS bus line will append lots of condensive load in the rated voltage , so when testing the GIS bus line voltage transformer , the booster is not allowed .

用数值计算方法详细模拟了室温及低温（77K）下VLSI电路中金属互连线的寄生电容和时间延迟，得到了金属互连线的几何结构对寄生效应的影响。

Parasitic capacitance and time delay for the interconnect in VLSI circuits at room temperature and 77 K are numerically simulated .

一种减少VDMOS寄生电容的新结构

New VDMOS Structure with Reduced Parasitic Capacitance

因此，器件设计者可以根据计算结果选择最合适的器件参数，设计出满足需要的最小寄生电容的MOS器件。

Therefore , according to the results , the device designer can select the most appropriate parameters to design a MOSFET with the minimum parasitic capacitances .

通过实验和理论分析可以证明，其主要起因是IGBT的寄生电容。

This may be caused by many factors , and the parasitic capacitance of IGBT is proved to be the key by the experiment and the analysis .

将寄生电容非灵敏有源开关电容网络（SCN）划分成若干个子网络，对每个子网络定义了运放负端组元割集；

The parasitic-insensitive active switched capacitor network ( SCN ) is partitioned into several sub-networks . Each subnetwork is defined as the op. amp .

对寄生电容不灵敏的开关电容有源FDNR滤波器的设计

Design of Parasitic-capacitance Insensitive Switched-Capacitor Active FDNR Filters

考虑到寄生电容的影响和工艺偏差，论文中还提出了耦合电容误差校准算法，并引入权电容失配校准算法，用以提高ADC的精度。

When considering the parasitic capacitors and process variation , the coupling capacitor calibration algorithm and the binary weighted capacitor mismatching calibration algorithm were also proposed to improve the accuracy of the ADC .

跨阻放大器设计采用了有源电感并联峰化和噪声优化技术，克服了CMOS光检测器大寄生电容造成的带宽不够的问题。

Active inductor shunt peaking technology and noise optimization are used in the design of a trans-impedance amplifier , which overcomes the problem of inadequate bandwidth caused by the large parasitical capacitor of the CMOS photodiode .

MOSFET非本征部分产生寄生电容会影响器件的性能，如何降低寄生电容的大小，一直是国内外学者的研究热点。

The extrinsic of MOSFET cause parasitic capacitance will affect the performance of the device , how to reduce the parasitic capacitance has been a hot topic to domestic and foreign scholars .

通过改变MOS变容管的接入方法实现了更好的压控增益线性度，并采用了新的低寄生电容、低导通电阻的数控电容阵列结构来补偿工艺变化带来的频率变化。

A novel configuration of a MOS varactor is designed for good linearity of Kvco , as well as a new digital capacitor controlled array topology with lower parasitic capacitance and lower Ron .

随着VLSI向深亚微米发展，需要快速而精确地计算互连寄生电容以保证高性能电路设计的正确性。

With development of the VLSI circuits towards the deep submicron , it is in great need of calculating the parasitic capacitance quickly and precisely to gain correct design of circuits with high performance .