地址总线

地址总线的功耗是DSP功耗的重要来源。

The power dissipated by the address bus is the important power dissipation source of the DSP .

大容量数据存储：采用两级Flash存储器组合使用，利用相同的数据、地址总线统一寻址。

Large data capacity . Two level FLASH is combined with same data and address bus .

DSP程序地址总线低功耗分段Gray编码方法

A Low-power Segmented Gray Coding for DSP Program Address

无数据地址总线端口的MOTOROLA系列单片机与外部存储器的并行接口技术

Technique of Parallel Interface with External Memory Using MOTOROLA Microprocessor

AO线通常被连结到地址总线的最低有效位。

The AO line is usually tied to the least significant bit of the address bus .

经功耗分析，DSP的程序地址总线功耗降低了73.2%，数据的地址总线和数据总线功耗降低了45.88%。

The power of program address buses is reduced up to 73.2 % , and the power of data address buses and data buses are reduced by 45.88 % .

在模拟器测控系统中，把单片机系统定义为包括：主频振荡器、看门狗和EEPROM、RS232接口、CPU、数据总线驱动器和地址总线锁存器。

In monitoring and control system of the simulator , the SCM system is defined as including : frequency oscillator , watchdog and EEPROM , RS232 interface , the CPU data bus and address bus driver latch .

通过可编程并行接口芯片8255将IBMPc并行打印端口扩展成3个具有双向通讯功能的8位I/O端口，利用这3个I/O端口分别作为数据采集仪器的数据总线、地址总线和控制总线。

The parallel print ports of IBM-PC can be extended to three bi-directional 8-bit I / O ports by a programmable integrated circuit chip named 8255 . The three I / O ports can be used as data bus , address bus and control bus of the data-acquisition instrument .

通过对PowerPC结构的总线协议的分析，总线接口部分主要由指令预处理部分、地址总线处理部分、数据总线处理部分和数据后处理部分组成，完成微处理器和外部总线的数据交互。

It will become the basis of Shared Bus . Though the analysis about the PowerPC Bus , there are four parts in BIU : Instruction Pretreatment Part , Address Bus Treatment Part , Data Bus Treatment Part and Data Pos-treatment Part .

微处理器的数据总线和地址总线的带宽分别为多少？

What is the uP data and address bus width ?

存贮器布局就是地址总线各位的寻址平面图。

A memory map is the addressing plan for the address bus bits .

微处理机使用地址总线设定在存贮器中存贮的数据的地址。

The microprocessor uses the address bus to locate data stored in memory .

地址总线为数据传输指明内存位置（地址）。

The address bus specifies the memory locations ( addresses ) for the data transfers .

当访问内存位置或寄存器时，在地址总线上的真实的地址。

The actual address that is placed on the address bus when accessing a memory location or register .

采样后经A／D转换和时内部地址总线信号译码，控制轴角数字信号。

After sampling , the angle digital signal is controlled with A / D conversion and bus signal decode .

地址总线被处理器用来选择在特定外设中的存储器地址或寄存器。

The address bus is used by the processor to select aspecific memory location or register within a particular peripheral .

为了降低大负载地址总线的功耗，提出了一种新的低功耗自适应偏移量总线编码方法。

A novel adaptive-offset bus encoding method was presented for reducing the power dissipation of highly capacitive memory address bus .

系统总线的功能在逻辑上被划分为三部分：地址总线、数据总线和控制总线。

The system bus is divided into three logical functions ; the address bus , the data bus and the control bus .

在系统仿真分析中，对地址总线、数据总线以及读写信号进行了详细的说明。

During the analysis of system simulation , the address bus , the data bus and the write / read signals are explained in detail .

使用预充电指令的缺陷在于，需要命令和地址总线在合适的时间处于可操控状态时，才能够发出预充电指令。

The disadvantage of the PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command ;

其中，总线低功耗编码分为应用于地址总线和应用于数据总线两种，串扰抑制编码有空间编码和时间编码两种编码策略。

Low-power bus coding methods can be divided into methods applied to address buses and ones applied to data buses . Crosstalk avoidance coding methods have two encoding strategies , i.e. spatial encodings and temporal encodings .

DMA有专用的片内地址和数据总线，所有DMA访问都通过DMA的专用总线，并且由DMA控制器控制。

DMA controller has dedicated on-chip address bus and data bus for DMA transfers , which are controlled DMA register .

多路传送地址与数据总线

Multiplexed address & data bus

显示所有IRQ号和内存地址，就象PCI总线上的卡看到的一样，而不是内核看到的内容。

Show all IRQ numbers and addresses as seen by the cards on the PCI bus instead of as seen by the kernel .

利用复杂可编程控制逻辑（CPLD）设计了系统控制逻辑、地址产生器、数据地址总线隔离器。

The system control logic , the address generator and the data bus separator are designed with a complex program logic device ( CPLD ) .

电路方面，文档录入机的控制电路和USB接口电路是整个系统设计的重点，而USB与文档录入机的信号采集共用数据线和地址线，因此数据和地址总线仲裁是设计的难点。

In the circuit aspect , it record into with document the semaphore of the machine collect to use the data wire totally and address wire , avoid the data and the clash of address is to design a little bit difficult .

在一片CPLD中集成了低位地址锁存、地址译码、数据总线、分频电路、比较、记数以及逻辑电路等。

It integrated flip-latch , coding unit , data bus , frequency division unit , logical compare unit , counter and logic circuit into a single CPLD chip , and dramatically decreased PCB 's area and increased system reliability .

地址选通用来指示有效的地址及新的总线访问的开始。

Address strobe indicates valid address and the start of a new bus access .

提出了一种新的低功耗非冗余排序总线编码方法，通过对改进的偏移地址线的动态重排以降低具有高负载的地址总线的功耗。

The irredundant sorting bus encoding method reduces the power dissipation of highly capacitive memory address bus based on the dynamic reordering of the modified offset address bus lines .

服务总线地址表示支持所需接口的服务的位置，该地址与服务总线对象一起被传递给代理对象，以使它能发送消息。

A service-bus address representing the location of the service that supported the required interface was passed to the proxy object , along with a service-bus object so that it could send messages .