位同步

一种抗衰落的位同步设计和FPGA实现

Design and FPGA Implementation of a Anti-fading Bit Synchronization Method

一种基于FPGA的新型快速位同步系统设计

A New Fast Bit Synchronization System Design Based on FPGA

基于早迟门位同步环的FPGA实现

Bit Synchronization Loop Based on Early-late Gate by FPGA

用FPGA实现的位同步电路

Design of Bit Synchronizing Circuit by Using FPGA

基于FPGA的位同步信号提取

Extraction of Bit Synchronization Signal Based on FPGA

一种基于FPGA的硬件开环位同步电路设计与实现

FPGA Based Open Loop Hardware Bit Synchronizing Cuit

基于FPGA的多模式通信信号解调及自适应位同步技术

The Demodulation of Multi-mode Communication Signals and the Adaptive Symbol Synchronization Technique Based on FPGA

设计调试了基于PCI接口的位同步器。

Design and implement the circuit board based PCI interface .

基于FPGA的FM解调/位同步系统设计与实现

Design and Implementation of FM Demodulation and Bit Synchronizer System Based on FPGA

采用FPGA实现了超短波跳频电台同步系统中的相关检测及位同步系统。

The FPGA were applied in the correlation detection and bit synchronous system of ultra_shortwave hop_frequency transceiver .

用CPLD器件实现24位同步计数器的设计

Designing 24 bit in Phase Counter by CPLD

FH／DS通信系统的位同步研究

Study of Bit Synchronization in FH / DS Communication System

基于FPGA的提取位同步时钟DPLL设计

Design of DPLL for Bit Synchronous Clock Based on FPGA

一种快速位同步的VHDL实现

Realization of a Fast Bit Synchronization Based on VHDL

本文提出了一种基于FPGA的快速同步捕获方案，该方案采用相关峰尖锐的巴克码组作为帧头，帧同步捕获的同时实现位同步。

In this paper , a new rapid synchronization algorithm based on FPGA is proposed , which can accomplish symbol timing and frame synchronization synchronously .

针对短时突发数据接收对位同步电路的要求，设计一种基于FPGA的硬件开环位同步电路。

A hardware electrocircuit scheme for bit synchronization are designed to met the demands of bit synchronization little paroxysmal data receiving in wireless digital system .

GPS接收机的关键技术主要有五项，依次为GOLD码捕获技术、GOLD码跟踪技术、载波跟踪技术、位同步技术和帧同步技术。

The five key technologies of GPS navigation receivers are Gold code acquisition technology , Gold code tracking technology , carrier tracking technology , bit synchronous technology and frame synchronization .

USB的电气特性反映了端口驱动电路、传输电平、编码结构、位同步处理及供电方式。

The USB electrical specifications describe the port driver circuit , electrical level of data transmission , code structure , bit synchronization and power distribution .

为了实现GMSK信号解调，接收机中DSP实现了调制信号的误差频谱估计、位同步恢复及译码。

To demodulate GMSK signal , DSP is used in receiver to achieve error spectrum estimation , bit synchronization recovery and decode .

并选用低噪声、低功耗的12位同步采样AD转换芯片进行采集电路设计，既保证了系统的信噪比，又提高了系统测量精度。

Secondly , the system has a good SNR and high accuracy , which is own to the application of low noise , low-power , simultaneous sampling 12-bit A / D converter .

本课题是便携式遥测跟踪接收系统的一部分，主要完成的是遥测跟踪接收系统信号处理硬件平台的设计与实现，以及基于PCI接口的位同步器的设计与实现。

As a part of ADAS , author have designed , drew up and implemented signal processing hardware equipments and a code timing recovery circuit based PCI interface .

不但详细描述了该方法的算法原理，而且还用FPGA技术通过VHDL硬件描述语言编程实现了该位同步提取方案。

This paper not only makes a detail description of the arithmetic theory of this method , but also realizes the bit synchronization scheme with FPGA by VHDL programming .

首先将接收到的PCM数据流进行位同步，然后经过一双口RAM作为缓冲，直接送入微机进行实时帧同步码粗同步。

PCM stream which has been bit blocked is sent into computer , buffered by a dual port static RAM , then it 's frame blocked roughly .

还重点研究了解调技术中的位同步算法，即Gardner位同步算法及其简化算法。

The paper also emphasized studies the bit synchronization algorithm of the modem , including Gardner algorithm and its simplified algorithm .

HDL是设计数字逻辑电路必不可少的通用工具，该文给出了位同步性能较好的积分型自同步的一个HDL实现。

HDL is an essential general tool in digital logical circuit design . A HDL implementation of the integral bit synchronization with good performance is provided .

本文推导了基带PAM（脉冲幅度调制）信号的互相关函数，指出基带PAM信号的互相关函数中含有位同步信息，以此为依据得到了一种位同步检测算法。

This paper derives the cross correlation function of baseband PAM ( Pulse Amplitude Modulation ) signal , and shows that the cross correlation function includes timing information .

最后分析了影响MSK解调器性能的因素：载波同步、位同步、帧同步。

Lastly , the effect of carrier synchronization , bit synchronization , frame synchronization on the performance of the modulation is studied .

提出了利用雷达chirp信号通过匹配滤波器实现快速、可靠位同步的方法，进行了相应的理论分析和计算机仿真，证明这是一种快速、可靠的位同步方法；

A scheme to use radar chirp signal passing through matched filter to implement quick and reliable bit synchronization was proposed , and some related computer-based simulations was also finished .

重点研究了突发GMSK中频信号的调制、差分解调、位同步和帧同步的设计方法及实现过程。

The design and implementation of modulation , difference demodulation , bit and packet synchronization of burst GMSK IF signal is emphasized .

在此基础上研究了PCMA系统中位同步误差对干扰抵消性能的影响，并给出了相应的仿真结果。

Interference cancellation performance degradation caused by timing error in PCMA System is then analyzed and simulated .