译码器

高存储效率的MAP译码器网格信息更新实现方法

Memory-efficient path metric update method in MAP decoder implementation

提出了一种新颖的MAP译码器结构。

In this paper , a new architecture of MAP decoder is presented .

TCM的全并行维特比译码器的设计及实现

A Design and Implementation of All-Parallel Viterbi Decoder Suitable for TCM

嵌入式可重构DSP处理器的指令译码器设计

Design of Instruction Decoder of Reconfigurable Embedded DSP Processor

Turbo译码器的logMAP算法及其实现

Log_ MAP Algorithm and Its Implementation of Turbo Decoder

基于FPGA的级联码的译码器的硬件设计

The Hardware Design of Concatenated Decoder Based on FPGA

一种用于IP包差错控制的RS译码器及其FPGA实现

A RS Decoder for IP Block Error Correction and Its Implementation on FPGA

该方法能提高原捕错译码器的纠错能力，可以识别C（x）中的码型（对偶码和非对偶码）。

The new method can improve error-correcting capability of old Error-Trapping Decoding , and identify form of code C.

基于复数基的RS译码器的FPGA优化实现

Optimized FPGA implementation of RS decoder based on composite basis

Turbo码译码器的定点DSP实现

Implementation of Turbo Decoder Implemented on a 32 Bit Fixed Point DSP

这种译码器有两个基于LOGMAP算法的分量译码器，这两个分量译码器交替的处理数据，最终完成译码。

Our turbo TCM decoder has two component log-MAP decoders , which perform the decoding process alternatively .

RS（255247）译码器的FPGA实现

Implementation of FPGA for RS ( 255,247 ) Decoder

基于FPGA的Turbo码译码器设计与实现

Design and Implementation of Turbo Decoder Based on FPGA

Turbo译码器的改进算法及FPGA实现

Improved decoding algorithm and FPGA-based implementation of Turbo coder

光存储RS译码器设计与译码速度分析

Design and Speed Analysis for an Optical Storage RS Decoder

RS码多路并行译码器的容错设计

The Fault Tolerant Design or Parallel Decoder for RS Codes

高速RS译码器的FPGA设计与实现

FPGA Design and Implementation of High-Speed RS Decoder

基于DSP实现的8状态turbo码译码器

A DSP-based Implementation of a 8-state Turbo Decoder

Turbo乘积码的两种迭代译码器的比较

Comparison between Two Classes of Iterative Decoder for Turbo Product Codes

最后给出了DSP芯片实现RS译码器的方法。

The method to implement the RS decoder with DSP processor will also be given .

基于CPLD的巴克码信号发生器与译码器

The Signal Generator and Encoder of Bark Code Based on CPLD

跳频系统中Turbo码译码器的FPGA实现

FPGA Implementation of Turbo Decoder in Frequency-Hopping System

使用RS译码器的编码方法研究

Study on encoding of RS codes with RS decoders

本文把P型动态电路与静态译码器结合，不仅解决了静态译码器的写重叠问题，而且提高了译码速度。

We combine a p-type dynamic circuit with a static decoder to solve the write-overlap problem in static decoder , and promote the decoding speed .

卷积码Viterbi译码器的FPGA的设计与实现

The FPGA Design and Implementation of Viterbi Decoder for Convolutional Codes

本文以某型号接收机的应用为背景，主要论述了如何实现基于FPGA的参数化的Viterbi译码器的知识产权（IP）核。

In this paper , a parameterized Viterbi decoder based on FPGA is presented .

宽带CDMA系统Viterbi译码器FPGA实现研究

The Research of Viterbi Decoder with FPGA in W-CDMA System

根据状态寄存器的情况，主从译码器对体系中可重置IP进行复用，实现安全通讯功能。

According to the situation of state register , principle and subordinate decoder can reuse IP to realize security communication .

流水线结构RS（255223）译码器的VLSI设计

A VLSI design of pipeline rs ( 255,223 ) decoder

利用CMOS模拟电路设计实现的新型概率译码器

Novel Probability Decoder Designed by CMOS Analog Circuits