功耗

SoC低功耗技术的另一个重要研究方向就是功耗动态管理的设计。

Dynamic management of power dissipation is another key research direction in SoC design field .

最后介绍了计算系统功耗的方法和芯片散热设计的注意事项。

The method for calculating power dissipation and some cautions for thermal design are provided in the end .

利用SAW技术实现极低功耗无线数字通信

Ultra-low Power Comsumption Wireless Digital Communication Using SAW Technology

针对目前各种键盘和LED控制驱动芯片功耗大的问题，介绍了一种基于低功耗设计的LED控制驱动及键盘接口模块。

This paper introduce the keyboard and LED driver based on design of Low Power Consumption .

基于超窄数据的低功耗数据Cache方案

A Low Power Data Cache Design Based on Very Narrow-Width Value

根据DesignPower分析其综合后门级实现结果，芯片面积可减少8%，功耗可减少51%。

According to the results analyzed by design power , the proposed methods can achieve 51 % power reduction and 8 % area reduction to the conventional ways .

高性能低功耗微控制器IP软核设计综述

An Overview on the Design of Microcontroller IP Soft Core with High Performance and Low Consume

基于记录缓冲的低功耗指令Cache方案

A Low-Power Instruction Cache Design Based on Record Buffer

一种低功耗、高线性、双正交可调谐CMOS上变频混频器

A Low-Power , High-Linearity and Double-Quadrature Tunable CMOS Up-Conversion Mixer

基于分类访问的低功耗联合式cache方案

Low-power united cache design based on classification access

这种方案在尽少占用DSP资源的情况下，可以低成本、低功耗和高品质的显示彩色数字图像。

The method can display color image with lower cost and power via little resource of DSP .

RFID门禁机的软硬件低功耗协同设计

Low Power Coordination Design of Rfid Door Access Machine 's Software and Hardware

稳定低功耗CMOS延时电路

A Stable , Low - Power CMOS Delay Circuit

CMOS数字电路的速度功耗优化设计

Optimal Design of High-Speed / Low-Power CMOS Digital Circuits

SOC时代低功耗设计的研究与进展

Research and Progress of Low Power Design in SOC Era

行为逻辑层上的SOC低功耗设计

Energy Efficient SOC Design Techniques at Behavioral and Logical Level

高性能低功耗带RAM的串行时钟芯片

The High Property and Low Power Consumption Serial Clock Chip with RAM

一个面积和功耗优化且适用于10/100Base-T以太网的CMOS时钟恢复电路

Power and Area Efficient CMOS Clock Recovery Circuit for 10 / 100 Base-T Ethernet

系统级CMOS电路的低功耗设计

System Level Low Power Design in CMOS Circuit

一种低功耗CMOS分频电路设计技术

A low power dissipation CMOS divider design technique

低功耗的可重构数据Cache设计

Low power reconfigurable data cache design

0.18μMCMOS高速低功耗分接器设计

0.18 μ m CMOS High-Speed Low-Power Demultiplexer

在CMOS工艺上进行射频电路设计成为可能，并逐渐成为低功耗、低成本射频集成电路的设计趋势。

The RF integrated circuits design based on CMOS is possible and became more popular .

基于可编程门阵列（FPGA）器件实现了低功耗的高速光互连链路。

A low power-dissipation gigabit-per-second optical interconnection data link was realized using field programmable gate array ( FPGA ) .

异步VLSI电路的低功耗技术研究

The Research of the Low - Power Technology Using Asynchronous VLSI Circuits

采用0.6μMCMOS工艺设计了一种低压低功耗的运算放大器。

A low-voltage and low-power CMOS op-amp was designed using a 0.6 μ m CMOS process .

一种新型高速低抖动低功耗双模预分频器及其在PLL频率综合器中的应用

A Novel High-Speed Lower-Jitter Lower-Power-Dissipation Dual-Modulus-Prescaler and Applications in PLL Frequency Synthesizer

低频、低功耗CMOSLNA的设计优化技术

Low frequency and low power CMOS LNA design optimization techniques

低电压低功耗CMOS采样保持电路

Low-Voltage Low-Power CMOS Sample-and-Hold Circuit

最大功耗估计问题是一个NP难题。

Maximum power estimation is a NP-hard problem .