分频电路

本文主要研究高速分频电路及其应用。完成了一种电流模式逻辑（CML）分频器设计，电压输出近似为满摆幅，可以直接和CMOS逻辑电路相连而不需要电平移位电路。

This work mainly focused on research of high speed frequency divider and its application . A current mode logic divider with nearly full voltage swing was designed . The divider could be directly connected to CMOS logic without level shifter circuit .

一种低功耗CMOS分频电路设计技术

A low power dissipation CMOS divider design technique

通过合理设计前端双模预分频电路、可编程P计数器和S计数器可实现任意分频比。

The random divide ratio can be get with the help of designing the dual-modulus prescaler , programmable P counter and S counter exactly .

给出了一种基于FPGA的等占空比任意整数分频电路的设计方法。

This paper gives out a design of the equal duty ratio arbitrary integer frequency divider based on FPGA .

采用8阶开关电容滤波器和CPLD所设计的分频电路，设计了一跟踪滤波电路。

A tracking filtering circuit is successfully developed by using a 8th-order switched-capacitor filter and dividing-frequency circuit based on CPLD .

基于查找表LUT结构的奇数与小数分频电路设计

Design of Odd and Decimal Frequency Divider Circuit Based on LUT

本设计的7/8预分频电路中包括两级CML二分频电路、相位切换电路、切换控制电路和TSPC二分频电路。

The 7 / 8 prescaler is composed of CML divider , phase-switching circuit , phase-switching-control circuit and TSPC divider .

通过单个反相器、100级反相器链，101级环振电路与210分频电路和一个大规模的SRAM电路来验证了提取的模型参数的有效性和实用性。

Through a single inverter , 100 inverter chain , 101 ring oscillator circuit , 210 frequency circuit and a SRAM circuit to verify the extracted model parameters is effective and practical .

在一片CPLD中集成了低位地址锁存、地址译码、数据总线、分频电路、比较、记数以及逻辑电路等。

It integrated flip-latch , coding unit , data bus , frequency division unit , logical compare unit , counter and logic circuit into a single CPLD chip , and dramatically decreased PCB 's area and increased system reliability .

晶体管双侧同步分频电路的研究正交频分复用中的符号同步技术

Study on the technique of symbol synchronization in OFDM systems

一种新的非整数分频电路的实现

A New Way to Attain a Non-integer Divider Circuit

安全、稳定的二分频电路设计。

Security and stability in the two-frequency circuit design .

振荡器和控制电路中尖峰脉冲噪声抑制、两分频电路及死区时间设定；

The analysis of spike pulse noise rejection , frequency divider and dead time in oscillator and control circuit ;

如果在这种情况下，其解决方案也会定义出需要什么样的附加时钟分频电路。

If this is the case , the solution will also specify how much additional clock division is required .

小型，低阻抗，高耐压电容，主要应用于音响分频电路。

Small , low impedance , the high pressure resistance electric capacity , mainly applies to the sound frequency dividing circuit .

在锁相理论指导下，第三章讨论了频率合成器设计中的鉴频鉴相器、数字滤波器、恒温压控振荡器和分频电路设计。

The designs of the PFD , digital filter OCXO and fractional-N counter in the frequency Synthesizer unit are discussed , based on the PLL theory .

本文研发了一种简单又适用的分频电路，引入电梯控制柜评估平台系统中，形成旋转编码器脉冲信号收集系统。

In this article , a simple and adaptable circuit about distinguishing frequency is introduced , which is developed in the system of collecting pulse signal information of pulse generator .

设计的方波激励磁通门接口电路，包括激励电路和检测电路两个部分，激励电路部分采用环形振荡电路和分频电路保证激励信号和相敏解调的基准信号的准确度。

The interface circuit includes two parts : the demodulation circuit and detection circuit . Ring oscillation circuit and frequency dived circuit are used in the stimulation circuit to reach the high accuracy .

锁相环设计又详细介绍了鉴频鉴相器、电荷泵、可变环路滤波器、分频电路以及失锁检测电路的设计。

While introducing the phase-locked loop circuit design , equipment of PFD , charge pump , variable loop filter , divider circuit and out of lock detection circuit design are also given detailed descriptions .

本文还设计实现了与时钟分布网络相关的模块电路，如频率保护电路、二分频电路、频率检测电路等，这些电路结构紧凑，大大提高了芯片的整体性能。

The paper also designed several key circuit modules in the clock distribution network , such as frequency protection circuit , halve frequency circuit , frequency detection circuit etc , all of those circuits ' structure is compact and their performance is high .

针对其为实现里程累计功能而设计的分频电路，阐述了机械速比、分频系数的计算方法，以及电子变速器电路与步进电动机驱动电路的设计方法。

According to the frequency dividing circuit designed for distance accumulating , this paper expounds the counting ways of mechanical velocity ratio and frequency dividing coefficients and the designing ways of the circuit of the electronic gearbox and the driving circuit of the stepping motor .

0.6μMCMOS静态分频器电路设计

Static Frequency Divider Circuit Design Using 0.6 μ m Standard CMOS Process

分频器电路采用0.18μMCMOS工艺设计，用于WCDMA通讯系统中。

The frequency divider implemented in a 0.18 μ m CMOS process is used in WCDMA system .

本文研制出多触头微波探针，建立了微波探针在片检测系统.针对GaAs高速集成电路&动态分频器电路芯片进行了在片测试和筛选。

Abstract The on-wafer testing system with microwave probe has been made and used to test the GaAs high-speed dynamic frequency divider chips on wafer .

第五章介绍了各控制电路在CPLD中的实现，重点阐述了分频时钟电路、译码电路、触发识别电路、限定识别电路、触发与存储控制电路及计数器电路的设计。

Chapter 5 describes the realizing of control circuits in CPLD . This section discusses the procedure that use graphics and AHDL to design clock circuit , decode circuit , trigger word distinguished circuit , limit word distinguished circuit , trigger and storage control circuit and counters circuit .

音响分频网络电路用铝电解电容器的研制

Development of Aluminum Electrolytic Capacitor for Audio Frequency Division Circuits

四倍分频器电路演化实验结果验证了该方法的可行性与有效性。

Experiment of fourfold frequency divider proved the feasibility and validity of the method .

本文中，首先讨论了目前主流的微波测距理论，然后应用Lattice1016对微波测距仪的部分分频控制电路进行了集成，并进行了功能仿真。

In this paper , the microwave ranger finder adopts two Lattice 1016 PLD chips to integrate some separate circuits and make the function simulation .

同时，借助于可编程鉴相器和分频器电路将信号频率点数字化、精确化。

At the same time , Recuring to the programed phase discriminator and frequency divider , the value of work frequency was scaled with digit accurately .

高速吞脉冲程序分频器的电路设计与PSPICE模拟

Design of a High Speed Pulse Swallow Programmable Frequency Divider and Its PSPICE Simulation