主存储器

这样的数据不再保留在计算机的主存储器中。

This information is no longer retained within the computer 's main memory .

以及能否有效地利用主存储器的容量。

as well as the amount of main memory it can use effectively

主存储器（又称为内存、主存或简称存储器）

Main memory ( also called internal memory , primary storage , or just plain memory )

从主存储器读数据需要较多的CPU周期。

Reading the data from the main memory requires more CPU cycles .

Cache实验中的主存储器接口设计

Interface Design of Main Memory for Cache Experiment

论述了主存储器访问操作中的bank预充电、row激活、column读写的访问调度技术。

A memory access scheduling is discussed in this paper . Memory access includes bank precharge , row activation and column access .

DMA控制器使I/O口和主存储器之间的数据直接进行读写，无需CPU的干预，系统总线由DMAC控制。由于数据不要经过CPU的中转，因此数据传送速度很高。

DMAC makes the data transfer directly between I / O port and main memory without CUP control .

当CPU下次读取相同地址时，数据将从高度缓存中而不是主存储器中传出。

The next time the CPU reads the same address , the data is transferred from the cache memory instead of from main memory .

CPU的设计会影响到计算机的处理能力和速度，以及能否有效地利用主存储器的容量。

The design of the CPU affects the processing power and the speed of the computer , as well as the amount of main memory it can use effectively .

SPE的存取指令及载入和存储指令将访问其私有LS，而不访问共享主存储器；LS没有关联缓存。

An SPE 's instruction-fetches and load and store instructions access its private LS rather than shared main storage ; the LS has no associated cache .

设置一个快进慢出RAM，先将模数转换的结果高速写入这个高速缓存器中，然后再传送到主存储器。

Setting a " quick enter slow out " RAM , it first write the ADC result to the high speed buffer and then send to the host computer main memory .

如果数据或指令没有出现在高速缓存中，或者如果高速缓存线路无效的时候，CPU通过从主存储器中读数据来更新它的高速缓存。

If the data or instruction is not present in the cache , or if the cache line is invalidated , the CPU updates its cache by reading the data from the main memory .

DDR存储器作为处理器的片外主存储器，是一种高性能、低成本的存储解决方案。

DDR memory is a kind of high performance and low cost memory solution , as a main external memory of the central processing unit ( CPU ) .

基于TEC-2主存储器扩展板的改进设计

Improving design to TEC-2 main memory extended broad

SPE用直接内存访问（DMA）命令访问主存储器，可以在主存储器与称为本地库或本地存储（LS）的私有本地内存之间移动数据和指令。

The SPEs access main storage with direct memory access ( DMA ) commands that move data and instructions between main storage and a private local memory , called a local store or local storage ( LS ) .

PPE用载入和存储指令访问主存储器（有效地址空间），可以在主存储器与内容可以缓存的私有寄存器文件之间移动数据。

The PPE accesses main storage ( the effective-address space ) with load and store instructions that move data between main storage and a private register file , the contents of which may be cached .

重点介绍了两页式转置存储器结构的典型应用，给出了以双数据率同步动态内存（DDRSDRAM）作为主存储器构成的两页式转置存储器的电路结构和实现结果。

The representative application of the two-frame CTM is introduced predominantly , of which the implementation in circuit and the result are given with the Double Data Rate Synchronous Dynamic RAM ( DDR SDRAM ) served as the main memory .

SAILII采用自动混写指针的策略来解决块在主存储器和第二级存储器之间移动时的指针管理问题。

Auto mix writing pointers used in SAILII solves the problem of moving blocks between the main memory and the second level storage devices .

PC机主存储器组成结构分析与设计

Analysis and Design for Main Memory Composition Structure of PC Machine

高速缓存是最靠近处理器执行单元的存储器，它比主存储器容量小得多，也快得多。

Caches are the memory closest to the processor execution unit .

在主存储器和后备存储器之间进行传输的过程。

The process of making transfers between main storage and backing storage .

个人计算机主存储器的发展及其容量的扩充

The Development of PC 's Main Memory and its extension of the Capacity

高档微机系统的主存储器扩增技术

The Expanding Technique of Memory for Supper Microcomputer Systems

不是计算机主存储器的数据存储装置。

A data storage device that is not the main memory of a computer .

通过把数据从主存储器复制到另一存储设备上去以保存数据。

To retain data by copying it from main storage to another storage device .

主存储器设计方法与技巧

Design Method and Technique of Main Memory

将主存储器中的数据复制到后备存储器中。

With respect to data in main storage , to copy it to backing storage .

主存储器又称为随机存取存储器，简称内存。

Primary memory is known as random access memory ( RAM ) and simple named memory .

最常见的处理件的部件是中央处理器和主存储器。

The most common components of processing hardware are the central processing unit and main memory .

表明主存储器分配给各输入输出设备和程序的一种图或表。

A drawing or table showing the allocation of main memory to input output devices and programs .