高速缓冲存储器

高速缓冲存储器控制通信

Cache memory control communication

可以在高速缓冲存储器策略中使用这个信息头来构建ID，而不必解析SOAP消息。

This header can be used in a cache policy to build IDs without having to parse the SOAP message .

这一页存入高速缓冲存储器了。

This page is cached .

通过在高速缓冲存储器内使用双端口SRAM，使其具有真正双端口并行访问能力，提高了处理器内核的数据吞吐能力。

With the utilization of dual-port SRAM , the data cache is dual ported to allow two accesses to proceed in parallel .

然后，可以使用cache-id从高速缓冲存储器中检索服务响应信息来使性能最优化。

The cache-id can then be used to retrieve service response information from the cache to optimize performance .

该处理机由16个处理单元和一个高速缓冲存储器组成一个一维线性阵列。

It consists of 16 cells and a cache connected linearly .

多机可缩放性高速缓冲存储器一致性协议分析

Analysis on Coincidence Protocol of Multi-CPU Machine 's Scaleable Cache

研究了这些算法和计算机芯片上纹理高速缓冲存储器的相互作用；

We will study how they interact with the on-chip texture cache .

32位微处理器的高速缓冲存储器和虚拟存储器

The Cache and The Virtual Memory in 32-bit Microprocessor

在高速缓冲存储器中找到所需数据。

The data needed is found in the cache .

计算机高速缓冲存储器体系结构分析

Analysis of Computer Cache Memory Architecture

解决处理器内核与访存之间的数据瓶颈，可以采用双Load/Store单元。为此，需要开发具有双端口访问能力的数据高速缓冲存储器。

Dual load / store units can be used to tackle the bottleneck between the processor core and the memory system .

并重点分析了进化存储系统中的关键技术，包括系统中内存管理的实现，高速缓冲存储器管理的实现和异构环境的数据共享。

Some key technique also is analyze , including Memory management realization this system , cache management realization and data share in the heterology environment .

用随机存取存储器的扇区存储因此能够访问磁盘的高速缓冲存储器。

A cache that stores copies of frequently used disk sectors in random access memory ( RAM ) so they can be read without accessing the slower disk .

本文论述了我们设计实现的有关高速缓冲存储器工作原理的教学动画演示系统。

In this paper , we discuss an animate-based courseware we designed and implemented , the Cache working principle teaching system made up of four parts : Cache working process module ;

如果自由高速缓冲存储器磁盘配额非常低，你有一些系统用户的号码，你要加个限制。

If the number of free cached disk quota entries is very low and you have some awesome number of simultaneous system users , you might want to raise the limit .

高速大容量FIFO缓冲存储器设计

Design of high speed and large scale FIFO cache memory