采样控制

采样控制系统数字PID参数寻优

The Optimization of the Digital PID Parameter of Sampling Control System

介绍了一种基于VC和Matlab的采样控制系统仿真。

Simulation of sampling control system based on VC and Matlab is introduced .

用TV摄象机对脉冲焊接电弧长度的采样控制

Study of sampling and controlling MAG welding arc length by TV camera

采样控制系统H∞设计方法及在飞行仿真转台中的应用

H ∞ Design Method for Sampled-Data Systems and Its Application in Flight Simulation Table

极点约束下采样控制系统H2控制问题研究

H_2-optimal sampled-data control with pole placement constraint

基于FPGA的高速并行A/D采样控制电路的设计

The Design of the A / D Sampling Control Circuit Basing on the High Speed Simultaneous FPGA

同时，由FPGA同步产生采样控制时序与电能质量分析控制时序，并在FPGA内部设计实现了采样数据缓存。

At the same time , FPGA produce the sampling control signal and the analyzing controlling signal simultaneously .

基于神经网络的液压AGC采样控制研究

Study on Sampling Control in Hydraulic AGC Based on Neural Network

PID算法和IFC算法在时滞性采样控制系统中的耦合与实现

Coupling and Realizing PID and IFC in the Time Delaying Sampling Control System

数控DC-DC变换器电流采样控制策略

Current sampling control strategy of digital control DC-DC converter

本文利用最小响应法给出了N≥2阶无静差采样控制系统的设计公式。

In this paper , by using the fastest response method , A formula for the design of N ≥ 2 order astatic sampled data control system is proposed .

基于采样控制系统直接设计理论的QFT设计方法及应用研究

Study on QFT Design Method and Application Applying Sampled-data Control Theory

讨论一种典型的采样控制系统&直接数字控制（DDC）系统（简称数控系统）在S域和P域的分析设计方法。

This paper discusses a method of analysis and design in of a typical sample control system-direct digital control ( DDC ) system S and P domains .

在同步采样控制中，采用实时采样方式，通过测量同步信号的频率，分频后控制ADC的采样频率，实现了多路信号的同步采样。

In synchronous data acquisition controlling , the multiple-channel synchronous sampling implemented by controlling ADC with divided frequency of synchronous signal in real-time sampling .

提出了一种新的采样控制系统的离散化H∞设计方法。

A novel discretization method of H_ ∞ design for the sampled-data control system is proposed and it is pointed out that the disturbance attenuation problem should be a constrained H_ ∞ optimal design .

介绍了一种以PIC单片机技术为核心的用于聚酯切片采样控制系统的设计。

A new type of polyester slice sampling controller was studied in this paper based on the method of self equilibrium control .

一块CPU负责采样控制和有效值的计算，另一块CPU负责保护处理和人机对话。

One CPU is in charge of sampling control and computing the effective value of signals , and the other is in charge of protection processing and dialog between users and CPU .

所提方案中，FPGA可完成对高速AD芯片的采样控制、读取采样值、计算共模电流的噪声能量值并将该值反馈给DSP。

In the plan mentioned , FPGA may complete to the high-speed AD chip sampling control , read the sampling value , and compute commom-mode current noise energy value and gives the value to DSP .

其中，总线接口，A/D采样控制，双端口RAM缓存，控制译码，时序逻辑电路均由CPLD实现。

In this instrument , bus interface , controlling of sampling of A / D , double port RAM , controlling coding , timing logic circuit are all realized by CPLD .

在对多种提升设计进行了对比分析后指出，提升方法并不能真正用于H∞优化设计，并给出了一种计算采样控制系统频率响应和L2诱导范数的方法。

And it is pointed out that the lifting technique is not suitable for H_ ∞ optimal design . A method for computing the frequency response and the L_2-induced norm of sampled-data control systems is given .

设计中通过FPGA实现对音频信号的采样控制，并将采样的数字信号转换为脉宽调制（PWM）信号，然后驱动H桥电路，实现功率放大。

In the design FPGA is used to control audio sampling and accomplish the conversion from digital audio signal to PWM signal , and then the PWM signal is used to drive the H-bridge for providing audio power output .

设计出了励磁方式控制子程序、A/D采样控制子程序、输入数据处理与流量计算子程序、键盘管理及LCD的汉字液晶显示等模块化程序。

As a result , the following subroutines are programmed : the optional excitation models , A / D sample , the flux processing and compute , the keyboard management , and the LCD display .

基于ISA总线的PC接口电路设计简单，可以实现高速ADC的启动控制、低速ADC的采样控制和缓存数据事后的传输。

The simple interface circuit is based upon the ISA bus , which can realize the start control of high-speed ADC , the sampling control of slow-speed ADC and the postmortem transfer of buffer data .

利用CPLD作为控制核心，设计一个基本双积分A/D转换器件的多路数据采集系统，详细分析A/D采样控制模块、计数模块、串口数据发送模块的实现。

A muti-channel data acquisition based on dual integration A / D converter is designed using CPLD the crux . The implementation of sampling controller unit , counter unit and serial interface output unit is detailed introduced .

其中，单片机主要实现AD采样控制、键盘按键控制以及向FPGA传送数据指令的功能；FPGA主要实现温度曲线拟合、PID控制算法以及PWM波形产生等功能。

Among them , the MCU mainly realizes functions of AD sampling control , keyboard keys control and transmitting data directive to FPGA ; FPGA mainly realizes functions of temperature curve fitting , PID control algorithm , as well as PWM waveform generator .

在驱动和控制模块中，采用Veriloghdl实现处理模块与传感器之间的采样控制、与SDRAM存储器以及与VGA显示器之间的时序要求。

In the drive and control modules , processing module using Verilog HDL to achieve between the sample and the sensor control , and meet the timing requirements of SDRAM memory and VGA display .

针对APF电流控制问题，提出了四种电流跟踪控制方法：周期采样控制，三角波比较控制，滞环比较控制和基于空间矢量的滞环控制方法。

Specific to current control problem in APF , the thesis proposes four kinds of current tracking control methods including periodic sampling control , triangle wave comparison control , hysteresis current comparison control and hysteresis control based on space vector .

系统软件部分主要由Verilog硬件描述语言实现，由数据采样控制模块、数据存储模块、数据处理模块三部分组成。

Part of the software is implemented through Verilog hardware describes language in the ISE integrated development environment , which is mainly composed of three parts sampling and controling module , memory module , lifting wavelet module .

数字变换单元是采用Veriloghdl硬件描述语言通过QuartusⅡ软件平台进行设计的，主要包括序列检测、A/D采样控制、CRC校验和异步收发等功能模块。

Digital conversion unit is used Verilog HDL hardware description language through the Quartus II software platform designed , Main sequence detection , A / D sampling control , CRC checksum function modules , such as Asynchronous Receiver Transmitter .

提出了基于CPLD和DSP构架的实时电能质量分析仪的设计，着重讨论了CPLD在实时电能质量分析仪采样控制电路优化设计中的应用，并讨论了非同步采样的同步化算法。

The design of real-time power quality analyzer based on DSP and CPLD is dis-cussed in this paper . The application of CPLD in the optimizing design of the sampling control circuit is analysed in detail , and the non-synchronization sample data 's isochronous algorithm is put forward .