卷积码

卷积码是Turbo码的基本组成单元。

Convolutional code is the basic component of Turbo code .

在3G中卷积码仍然是低速数据的信道编码。

Convolutional code is still the channel coding in low speed data transmission services in 3G .

卷积码的SYSTEMVIEW实现

The Implementation of Convolution Code in System View

基于（2,1，N）卷积码的网络丢包纠错方法

Method correcting network packet losses based on ( 2,1 , N ) convolutional code

卷积码的Matlab仿真及其性能研究

Performance Research and Simulation of Convolution Code Based on Matlab

基于FPGA的卷积码分组译码方法

Packet decoding method for convolutional codes based on FPGA

CDMA手机卷积码编码器的设计与FPGA的实现

Design of convolution-coder in CDMA mobile telephone and its realization of FPGA

卷积码采用分段编码和译码的方法，并以DSP为实现平台。

Convolutional encoding and decoding is accomplished by methods of fragmenting , realized in DSP .

TCM方案是以卷积码为基础的。

TCM scheme bases on convolution codes .

卷积码Viterbi译码器的FPGA的设计与实现

The FPGA Design and Implementation of Viterbi Decoder for Convolutional Codes

几个影响Woven卷积码纠错性能的因素

Some influential factors of Woven convolutional codes ' error correction performance

基于卷积码的DCT域音频扩谱水印算法

Spread-spectrum Audio Watermarking Algorithm in DCT Domain Based on Convolutional Codes

综合信道估计和卷积码的CDMA同频干扰消除技术

CDMA Co channel Interference Cancellation Utilizing Pilot Symbol Aided Channel Estimation and Convolutional Codes

卷积码编码及其Viterbi译码算法的FPGA实现

FPGA Implementation of Convolutional Code Encoding and Viterbi Decoding Algorithm

基于FPGA的删除卷积码Viterbi软判决译码器的研究

Research on FPGA-Based Soft-Decision Viterbi Decoder for Convolutional Codes Puncturation

Turbo码是并行级联递归系统卷积码。

Turbo code is the parallel concatenated convolutional code .

基于FPGA的卷积码Viterbi编码/译码器的设计与实现

The FPGA Design and Implement of Viterbi Encoder and Decoder for Convolutional Codes

卷积码Viterbi译码的FPGA实现

Convolution Code of the Viterbi Decoding FPGA to Achieve

Woven卷积码及其迭代译码算法

Woven Convolutional Codes and A New Iterative Decoding Algorithm

以（2,1,6）卷积码为例，介绍了卷积码的部分并利用SYSTEMVIEW软件将整个（2,1,6）卷积码实现。

Taking a ( 2,1,6 ) convolution code as example , the encoder and decoder are given and the whole ( 2 , 1 , 6 ) convolution code is implemented in System View .

本文建议了基于局部概率传播译码的低密度卷积码和RS码的级联方案。

This dissertation proposes the approach of concatenation of RS code and low density convolution code .

给出的神经网络译码器是为长约束度（K≥11）卷积码译码而设计的。

The neural network decoder presented in this paper is designed for long constraint length convolutional codes ( K ≥ 11 ) .

RS码、卷积码的软件实现与WCDMA试验网射频优化

Software Implementation of RS Codes & Convolutional Codes and WCDMA Trial Network RF Optimization

基于VHDL语言的卷积码编解码器的设计

Design of Convolution Encoder and Decoder Based on VHDL Language

通信系统中卷积码编解码器的VHDL实现

VHDL Realization of Encoder and Decoder for Convolutional Code in Communication System

最后介绍了卷积码和维特比译码的基本原理，具体介绍了维特比译码算法中的分支度量、路径度量和回溯跟踪三部分，译码算法由DSP芯片实现。

We research on the Trellis Paths , Metric Update and Traceback in Viterbi decoding . Decoding is realized by DSP chips .

基于AWGN多次迭代的Turbo码与卷积码性能比较

Capability Comparison Between Turbo Codes and Convolutional Codes in AWGN

Viterbi算法是卷积码最常用的译码算法。

Viterbi algorithm is the optimal decoding scheme for convolutional codes .

通常，WCDMA系统采用的信道编译码方案为卷积码，或Turbo码。

Generally WCDMA adopts convolution code or Turbo Code as its channel coding and decoding scheme .

一种卷积码的VITERBI译码的实现

Realization of VITERBI Decode of a Kind of Convolution Code