tlb
- 网络转换后备缓冲器;后援缓冲器;翻译后援缓冲器;快表;旁路转换缓冲
![tlb](../cache/557304.jpg)
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Research of the Key Technology for Low-Power TLB Design
低功耗TLB设计关键技术研究
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The Research on Reconfigurable SoC DFT Structure and TLB Test Scheduling Strategy
可重构SoCDFT架构与TLB测试调度策略研究
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Research on TLB Design Methodology of Embedded Processor
嵌入式处理器TLB设计方法研究
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But this design choice ignores the effect of TLB misses .
但是这样的设计忽略了TLB失配对系统性能的影响;
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Evaluation on fertility effect applied TLB microbial fertilizer
田力宝微生物肥料的肥效评价
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This is because TLB is able to map a larger virtual memory range .
这是因为TLB能够映射更大的虚拟内存范围。
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This research focuses on multi level set associative TLB performance of the general purpose microprocessor .
本文针对超深亚微米通用微处理器中的多级TLB设计开展研究。
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If there are too many TLB misses , your code read data in large address range .
如果发生了很多TLB失效,就说明代码读取大地址范围中的数据。
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The TLB on the critical path of microprocessor core contains data array and tag array .
微处理器内核关键路径上TLB由Data阵列和Tag阵列组成。
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Design and optimize of the TLB in Cache
Cache中TLB的设计及优化
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An innovation of multi-process TLB entry sharing one cacheline window .
多进程TLB表项共享缓存行窗口的设计方法。
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Select the type library from the available references list , or browse for the TLB file .
从“可用引用”列表中选择类型库,或通过浏览选择tlb文件。
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Design of TLB for Embedded Processor
嵌入式处理器的TLB电路设计
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TLB is the cache holding the mapping information from the virtual address to the physical page in memory .
TLB缓存包含从虚拟地址到内存中物理页面的映射信息。
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The performance improvements are due to the reduced translation look aside buffer ( TLB ) misses .
性能的提高归功于转换表缓存区(translationlookasidebuffer,TLB)失败的减少。
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When data is fetched or stored , the processor uses a separate data TLB for the translation .
当数据存取时,处理器会使用独立的数据TLB来进行翻译。
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This method partitions cacheline into different process windows to prevent frequency replacement of TLB entry during process switch .
通过将缓存行划分成不同的进程窗口,防止进程切换时TLB表项的频繁替换。
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This paper presents a structure of a TLB that can be rendered by a 32-bit general CPU .
文中介绍一种适用于32位通用CPU的TLB结构。
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The high performance and low power two-level TLB accessing mechanism was used to obtain high access speed and low TLB miss rate .
高性能低功耗两级TLB访问机制,实现了访问速度与访问容量的优势互补。
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In addition , a DVS technology is used reducing the leakage power in the TLB 's memory cells by 90 % .
此外,通过引入DVS技术将TLB存储单元中的漏电功耗减少90%以上。
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And the TLB uses fully associative placement generally , this make it become the focus of the microprocessor power dissipation .
随着单位面积内的晶体管数指数式增长,微处理器芯片的功耗也不断增加,而TLB一般采用的全相联结构使其成为微处理器中的功耗焦点。
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The use of large pages can also improve performance by reducing the number of translation lookaside buffer ( TLB ) misses .
大内存页的使用还可以通过减少变换索引缓冲(translationlookasidebuffer,TLB)的失败次数来提高性能。
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As a result , in this topic about study design of the TLB , the reusability and expandability become a point equally .
因而,本课题在研究TLB设计时,可重用性和可扩展性同样成为一个重点。
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A way combined based on-line configurable cache and 2-level TLB MMU micro-architecture is proposed in memory subsystem design .
内存子系统的设计中提出了基于组拼合的可在线配置Cache和两级TLB结构的全综合设计MMU。
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With Simple Scalar 3.0 , a simulation of the proposed TLB and some traditional TLB structures were made to observe the miss ratio .
并且采用Simplescalar3.0模拟该TLB结构和几种传统的TLB结构的失效率。
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Locking TLB entries can ensure that a memory access to a given region never incurs the penalty of a page table walk .
锁定TLB输入能确保对于给出区域的内存读取绝不会导致页表移动的掉失。
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The CAM enables TLB to speed up the virtual reality address translation through parallel and express comparison , which greatly impact on the microprocessor performance .
CAM通过并行快速比较支持TLB加速虚实地址转换。从而,它的速度对微处理器性能有很大的影响。
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Whenever an instruction is fetched from memory , the instruction pointer is translated via the instruction TLB into a physical address .
无论何时从内存中取一个指令,指令指针都会经指令TLB的翻译后指向物理地址。
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In order to speed up the address translation , the most modern processors have designed a hardware unit called translation look-aside buffer ( TLB ) .
为加快虚存的访问,现代高性能微处理器实现了一种硬件地址映射结构:转换后援缓冲器(简称TLB);
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Therefore , high-performance processor must optimize the TLB in order to reduce the address translation delay , only in this way can meet the system requirements of high-speed memory access .
因此高性能处理器必须通过优化TLB的性能,才能使地址变换的延迟满足系统高速访存的要求。