采样保持

采样保持电路内置于DAC，节省了电路开销和芯片面积。

Sample and Hold circuit built-in DAC saves circuit costs and chip area .

AGC环路中，采用了带共模反馈的VGA结构，包含一个改进的具有采样保持功能的峰值检测电路，并构造了一种新型的指数控制电路。

This AGC system adopts a VGA structure with CMFB and a peak-detect circuit having sample and hold function , and constructs a new-style exponential control circuit .

带采样保持功能的CCD驱动脉冲的设计方法

Design Method of CCD Driving Logic with S / H Function

一种全差分双通道采样保持的流水线操作AD变换器

A Pipelined AD Converter Based on Fully Differentiating Dual-tunnel Sampling / Holding Circuit

介绍一种用于流水线ADC的采样保持电路。

Introduction sampling-hold circuit of a pipeline used for ADC .

基于流水线ADC的采样保持电路的研究

Study of Sample-and-hold Circuit Based on Pipeline ADC

低电压低功耗CMOS采样保持电路

Low-Voltage Low-Power CMOS Sample-and-Hold Circuit

一种用于大面积CMOSFPA的相关双采样保持电路

A New Correlated-double-sampling Circuit for Large Format CMOS FPA

每个ADC均具有宽带宽、差分采样保持模拟输入放大器，支持用户可选的各种输入范围。

Each ADC features wide bandwidth differential sample-and-hold analog input amplifiers supporting a variety of user-selectable input ranges .

设计了一个用于SAR结构的模数转换器的采样保持电路，采用5V供电具有14bit的采样精度和4MHz的采样频率。

A 14-bit , 4 MHz sampling precision sample-and-hold circuit with 5V supply for SAR ADCs was designed .

第一部分为单元电路宏模型的构建，利用SPICE编程语言分别完成了采样保持电路、理想开关电路以及比较器电路的宏建立。

In the first part , the modeling of sample circuit , ideal switch and comparator using SPICE is completed .

这是一款完整的单芯片ADC，内置片内高性能、低噪声采样保持放大器和可编程基准电压源。

It is a complete , monolithic ADC with an on-chip , high performance , low noise sample-and-hold amplifier and programmable voltage reference .

详细分析了程控放大电路、峰值采样保持电路、V／F转换电路的工作原理，并给出了程序流程图。

The operation principles of programmable amplifying circuit , peak sampling , holding circuit and V / F converting circuit are analysed in detail and program flow graphic is also given .

所设计的ADC采用一种双采样保持电路降低了对折叠器的带宽要求，获得了优良的动态特性；

This paper proposes an ADC , which adopts a double-sampling circuit to minimize the bandwidth requirement of the folder and achieves good dynamic characteristics .

通过合理选配A/D、CPU等参数减少采样保持时间、A/D转换时间、数据传输时间与CPU计算时间等组成的数据转换过程的总时延，保证了系统的精确度。

Reasonable selection of A / D and CPU is very important for sharply shortening the period of sampling and holding , A / D conversion , data transmissions , and final calculation .

该谱仪的模数转换器采用带采样保持器的14位高速ADC芯片和带USB接口的16位单片机，简化了电路，提高了性能；

By taking fast 14-bit ADC with track / hold circuit and 16-bit microcontroller with USB interface , the circuit of the spectrometer analog-digital converter is simplified , and the performance is improved .

流水线ADC的模块有采样保持电路、乘法数模转换器、子ADC、数字校正电路、时钟产生电路和时间对齐电路。

The whole circuit consists of Sample and Hold Circuit , the Multiplicative A / D Converter , the Sub-ADC , the Digital Calibration Circuit , the Clock Generator and the Time Synchronizer .

在信号输入端采用了采样保持放大器（SHA）以提高信号-噪声失调比（SNDR）及ADC线性度。

A sample-and-hold amplifier ( SHA ) was used to improve the signal-to-noise and distortion ratio ( SNDR ) performance and the linearity of ADC .

而采样保持做为流水线型ADC的最前端部分，其速度、精度和功耗将决定着整体ADC的性能。

Sample / Hold Circuit ( S / H ) is the most forward part of Pipeline ADC , and its speed resolution and power consumption will mostly determine the performance of the whole ADC .

介绍了一种采用0.35μMBiCMOS工艺的双路双差分采样保持电路。该电路分辨率为8位，采样率达到250MSPS。

A 0.35 μ m BiCMOS dual-path-dual-difference sample-and-hold circuit is presented , which has ( achieved ) an 8-bit resolution and 250 MSPS sampling rate .

本文设计了基于CPU和DSP技术的高速、高精度数据获取及处理系统，利用多通道采样保持和分时转换电路实现数据的同步采集，主CPU和从DSP芯片间通过双口RAM进行信息交换。

A high-speed and high-precision distributed data acquisition and processing system is designed based on CPU and DSP in this paper . The synchronous data sampling of the supervising system is realized by multi-channel collection retaining and A / D transformation circuit .

在此基础上，设计了一个开环结构的采样保持电路，并运用CadenceSpectre软件对电路进行了性能分析和仿真。

Under the guidance of the theory mentioned , designs a Track-and-Hold circuit of open-loop architecture , then analyzes the performance and simulates the circuit using the Cadence Spectre software .

Flip-around结构高速采样保持电路的设计

Design of a High-Speed Flip-Around Sample-and-Hold Circuit

介绍管道灰垢层厚度X射线测量仪的研制，详述仪器键盘与显示、A/D转换与采样保持电路及传感器电路，讨论用连续宽束X射线进行厚度测量的特点和影响精度的诸因素。

X-ray thickness meter developed for the flyash scale in pipe is described including the keyboard . display , A / D , S / H circuits and transmitter circuit . Discussed also are the characteristics of thickness measurement with wide beam X-ray and the factors affecting measuring precision .

本文主要介绍用mcs-48系列单片机，配以采样保持、A/D、D/A转换和模拟输出驱动板，并采用PID算法进行调节，构成直接数字控制DDC调光、调温、调速系统。

This paper describes a light , temperature and speed adjusting DDC system which is composed of MCS-48 series computer , sample-and-hold circuit . In this DDC system PID algorithm is used as the controlling algorithm .

该滤波器采用多相插值原理，硬件电路包括并行数据输入接口、8倍插值器、16倍采样保持电路，实现对输入音频信号（PCM码）的128倍过采样。

The filter based on ployphase interpolation principle , consists of a parallel data input , a 8 × interpolator , a 16 × sample-and-hold circuit , to over-sample ( 128 ×) the audio signal ( PCM code ) .

采样保持电路是流水线型ADC中的关键模块。它位于转换器信号处理链的最前端，它的速度和分辨率决定了整个转换器所能达到的最大转换速度和最高分辨率。

Sample and hold circuit ( S / H ) is a critical module in pipelined ADC , which is located at the beginning of the signal processing chain . Its speed and resolution restrict the maximum conversion rate and maximum resolution of the ADC .

所设计的采样保持电路满足100MHz采样频率10位A/D转换器的性能要求。

Simulation results show that the S / H circuit has a good performance that meets the requirement of 10-bit A / D converter with 100 MHz sampling frequency .

重点分析了典型子电路模块：开关电容采样保持电路、亮度控制电路、振荡器、过温保护电路、PTAT和带隙基准电路等。

Typical sub-blocks were analysed emphatically such as Switch Capacitor Sampling / Holding Block , Brightness Control Block , Oscillator , Thermal Shut Down Circuit , PTAT and Bandgap Reference etc.

在信号输入端设置了采样保持放大器（SHA），级电路中采用了低功耗运算跨导放大器（OTA）和动态比较器，并且使用了采样电容优化技术和数字校正技术。

When sample-and-hold amplifier ( SHA ) was set at the input ports , low power dissipation operational trans-conductance amplifier ( OTA ) and the dynamic comparators were designed in the sub-stage circuits , and sampling capacitors optimization technique and digital correction technique were employed .