采样保持电路

采样保持电路内置于DAC，节省了电路开销和芯片面积。

Sample and Hold circuit built-in DAC saves circuit costs and chip area .

流水线ADC的模块有采样保持电路、乘法数模转换器、子ADC、数字校正电路、时钟产生电路和时间对齐电路。

The whole circuit consists of Sample and Hold Circuit , the Multiplicative A / D Converter , the Sub-ADC , the Digital Calibration Circuit , the Clock Generator and the Time Synchronizer .

介绍一种用于流水线ADC的采样保持电路。

Introduction sampling-hold circuit of a pipeline used for ADC .

基于流水线ADC的采样保持电路的研究

Study of Sample-and-hold Circuit Based on Pipeline ADC

低电压低功耗CMOS采样保持电路

Low-Voltage Low-Power CMOS Sample-and-Hold Circuit

一种用于大面积CMOSFPA的相关双采样保持电路

A New Correlated-double-sampling Circuit for Large Format CMOS FPA

设计了一个用于SAR结构的模数转换器的采样保持电路，采用5V供电具有14bit的采样精度和4MHz的采样频率。

A 14-bit , 4 MHz sampling precision sample-and-hold circuit with 5V supply for SAR ADCs was designed .

第一部分为单元电路宏模型的构建，利用SPICE编程语言分别完成了采样保持电路、理想开关电路以及比较器电路的宏建立。

In the first part , the modeling of sample circuit , ideal switch and comparator using SPICE is completed .

详细分析了程控放大电路、峰值采样保持电路、V／F转换电路的工作原理，并给出了程序流程图。

The operation principles of programmable amplifying circuit , peak sampling , holding circuit and V / F converting circuit are analysed in detail and program flow graphic is also given .

所设计的ADC采用一种双采样保持电路降低了对折叠器的带宽要求，获得了优良的动态特性；

This paper proposes an ADC , which adopts a double-sampling circuit to minimize the bandwidth requirement of the folder and achieves good dynamic characteristics .

介绍了一种采用0.35μMBiCMOS工艺的双路双差分采样保持电路。该电路分辨率为8位，采样率达到250MSPS。

A 0.35 μ m BiCMOS dual-path-dual-difference sample-and-hold circuit is presented , which has ( achieved ) an 8-bit resolution and 250 MSPS sampling rate .

在此基础上，设计了一个开环结构的采样保持电路，并运用CadenceSpectre软件对电路进行了性能分析和仿真。

Under the guidance of the theory mentioned , designs a Track-and-Hold circuit of open-loop architecture , then analyzes the performance and simulates the circuit using the Cadence Spectre software .

Flip-around结构高速采样保持电路的设计

Design of a High-Speed Flip-Around Sample-and-Hold Circuit

介绍管道灰垢层厚度X射线测量仪的研制，详述仪器键盘与显示、A/D转换与采样保持电路及传感器电路，讨论用连续宽束X射线进行厚度测量的特点和影响精度的诸因素。

X-ray thickness meter developed for the flyash scale in pipe is described including the keyboard . display , A / D , S / H circuits and transmitter circuit . Discussed also are the characteristics of thickness measurement with wide beam X-ray and the factors affecting measuring precision .

该滤波器采用多相插值原理，硬件电路包括并行数据输入接口、8倍插值器、16倍采样保持电路，实现对输入音频信号（PCM码）的128倍过采样。

The filter based on ployphase interpolation principle , consists of a parallel data input , a 8 × interpolator , a 16 × sample-and-hold circuit , to over-sample ( 128 ×) the audio signal ( PCM code ) .

采样保持电路是流水线型ADC中的关键模块。它位于转换器信号处理链的最前端，它的速度和分辨率决定了整个转换器所能达到的最大转换速度和最高分辨率。

Sample and hold circuit ( S / H ) is a critical module in pipelined ADC , which is located at the beginning of the signal processing chain . Its speed and resolution restrict the maximum conversion rate and maximum resolution of the ADC .

所设计的采样保持电路满足100MHz采样频率10位A/D转换器的性能要求。

Simulation results show that the S / H circuit has a good performance that meets the requirement of 10-bit A / D converter with 100 MHz sampling frequency .

重点分析了典型子电路模块：开关电容采样保持电路、亮度控制电路、振荡器、过温保护电路、PTAT和带隙基准电路等。

Typical sub-blocks were analysed emphatically such as Switch Capacitor Sampling / Holding Block , Brightness Control Block , Oscillator , Thermal Shut Down Circuit , PTAT and Bandgap Reference etc.

设计了一种低失真、高速的开关电容采样保持电路，采用了新型的bootstrapped开关来降低由于开关引入的非线性，并提出了减小放大器的建立时间以减小运算放大器引入的非线性的方法。

A low distortion , high speed switched capacitor sample and hold circuit has been designed . A novel bootstrapped switch is used to degrade the nonlinearity and the method to decrease the settling time of the amplifier is proposed .

模拟结果显示，其无杂散动态范围达到95dB，满足了A/D转换器采样保持电路对输入信号高动态范围的要求，也保证了电路的可靠性。

Results show that a spurious free dynamic range up to 95 dB has been achieved for the circuit , which satisfies the requirement of S / H circuit in A / D converters for large dynamic range , ensuring the reliability of the circuit .

低失真与高速采样保持电路的设计

The Design of Low Distortion High Speed Sample / Hold Circuit

设计了高性能宽带采样保持电路。

The high performance broadband T / H circuit is designed .

浅议化蛹抽查法对称开关电容采样保持电路的研究

An Investigation on the Sampling - Holding Circuit With Symmetric Switching Capacitor

对采样保持电路中电容失配的误差分析与仿真

Simulation and Analysis of Capacitor Mismatch Error in Sample and Hold Circuit

一种高速、低失真的采样保持电路

A High Speed 、 Low Distortion Sample And Hold Circuit

电路设计完成后，进行了采样保持电路的版图设计。

After the schematic is finished , the layout of the circuit is designed .

一个用于流水线模数转换器的高精度、低功耗采样保持电路

A High Resolution Low Power Sample and Hold Module Dedicated to a Pipelined ADC

详细讨论了采样保持电路等核心单元的设计。

Important blocks such as the Sample and Hold circuit are analyzed in detail .

设计了一个用于流水线型模数转换器的低压采样保持电路。

A low supply voltage sample-and-hold circuit for a pipelined analog-to-digital converter is described .

一种新型高速高分辨率采样保持电路

A New High-Speed and High-Resolution Sample-and-Hold Circuit