verilog
- 网络硬件描述语言;测试
![verilog](../cache/573244.jpg)
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The Development and Application of Two Hardware Description Languages-VHDL / Verilog
两种硬件描述语言VHDL/Verilog的发展及其应用
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The process of designing digital logic system by verilog HDL is presented , compared with the traditional digital logic system design method .
通过与传统的数字逻辑系统的设计方法进行比较,展现了硬件描述语言Verilog-HDL设计数字逻辑电路的优越性。
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High Level Design Environment for Digital Integrated Circuit Based on Verilog HDL
基于VerilogHDL的数字集成电路高层设计环境
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Analysis of several problems in digital circuit design by verilog HDL
用Veriloghdl设计数字电路过程中的两个问题
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Interface Design Based on Verilog Language in SoC Hardware Interface Synthesis
SoC硬件综合设计中基于Verilog语言的接口程序设计
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Design of High Speed Interface FPGA and USB 2.0 Based on Verilog
基于Verilog的FPGA与USB2.0高速接口设计
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Design and Test of CAN Bus Controller Based on Verilog HDL
基于Veriloghdl语言的CAN总线控制器设计及测试
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A Verilog HDL - based Pipelining Design Method and its Application
基于Veriloghdl的流水线的设计方法及应用
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How to Design a Digital System Using Verilog HDL
如何用Veriloghdl来设计数字系统
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Detection platform software components that Verilog language description logic . 2 .
检测平台软件部分即Verilog语言描述的逻辑设计。
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Research and Realization of Digital Image Sharpening Based on Verilog
基于Verilog的数字图像锐化研究和实现
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Research of SoC Functional Verification Based on System Verilog
基于systemverilog的SoC功能验证方法研究
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Implementation of LED Display Scanning Controller Model Based on Verilog HDL
基于Veriloghdl的LED显示屏扫描控制模块的实现
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Rules of CPLD / FPGA System Design Based on Verilog HDL
Veriloghdl语言在FPGA/CPLD系统设计中的几个原则
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Two Special Data Types in Verilog HDL and Evaluation of the Variables
Veriloghdl语言中的特殊数据类型及其赋值
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The Design Example of Verilog HDL and Its Simulation & Synthesis
Veriloghdl设计实例及其仿真与综合
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Implementation of PCI bus object interface status machine using Verilog HDL
PCI总线目标接口状态机的Veriloghdl实现
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The Frequency Measuring and Its Fulfilling Method Based on Verilog HDL
频率测量及其Veriloghdl的实现方法
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The Basic Methods of FPGA design using Verilog HDL
用Veriloghdl进行FPGA设计的一些基本方法
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The result of Verilog simulation , synthesis and static time analysis show the design is successful .
Verilog仿真、综合和静态时序分析的结果表明该设计达到了良好的效果。
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The third level is coding , simulation and validation of language Verilog .
Verilog语言代码的RTL级实现及其仿真综合验证;
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The RTL design of the module is completed using Verilog .
针对该芯片的架构,提出了缓冲器管理单元的设计方案,并应用Verilog语言完成了该单元的RTL级设计。
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Study of synthesis issues of Verilog language
Verilog语言综合问题研究
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The Verilog HDL has been used in the paper to describe whole algorithm .
在设计中本文使用了Verilog语言对整个个算法进行了描述。
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FPGA realization of SPWM entire digital algorithm based on Verilog HDL
基于Veriloghdl的SPWM全数字算法的FPGA实现
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Design of digital circuit based on Verilog HDL
Veriloghdl数字电路的设计
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Using Verilog language for programming , program is readability .
编程时使用Verilog语言,程序可读性强。
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Design of random clock error test bench in verilog
基于Verilog的随机时钟误差测试平台设计
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Design and Implementation of Single-precision Floating Point Multiplier Based on Verilog
基于VeriIog的单精度浮点数乘法器的设计与实现
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The design process is through advancing of algorithm and verification , Verilog design and verification .
整个设计过程经历了算法提出与验证,Verilog设计以及仿真验证。