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plls

  • 网络锁相环;锁相回路;锁相环电路;锁相回路设计
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  1. Design and Application of PLLs Repeater in Solar Energy System

    太阳能直放站锁相环系统设计与应用

  2. Phase-Accelerating Signal Acquisition Behavior of PLLs

    锁相环对相位加速度信号的捕捉性能

  3. The presented PFD can be widely used in high speed , low jitter and low spurious tones PLLs .

    这种差分型PFD在高速、低抖动、低假频PLL中有着广泛的应用。

  4. Phase-locked loops ( PLLs ) are widely used in high speed digital systems to generate low jitter on-chip clocks .

    PLL系统被广泛的应用于各种高速数字系统中,来产生低抖动片上时钟信号。

  5. Using an impulse function or a pulse to represent a single event hit on CPs , the SET analysis model is established and the characteristics of SET generation and propagation in PLLs are revealed .

    在确定了CP为整个PLL中最敏感部件的基础上,采用冲激信号和脉冲信号代替单粒子撞击CP,对SET进行了建模,揭示了SET的产生与传播特性。

  6. Distortion in digital phase / frequency detectors is one of the main factor in causing instability , spurious signals , and excessive phase noise in phaselocked loops ( PLLS ) .

    数字式鉴相器的相位失真是导致产生寄生信号和额外相位噪声并使锁相环路不稳定的主要因素之一。

  7. Because the demands of high performance and low cost are now the main challenges for SoC design , the design of phase-locked loops ( PLLs ) used as clock generators on chip becomes very critical .

    由于高性能、低成本已成为SoC设计的主要挑战,作为片上时钟发生器锁相环的设计变得非常关键。

  8. While as the key unit , voltage-controlled oscillator ( VCO ) generate the output clock signal of PLLs , and its identity directly decide the capability of the PLLs .

    而作为锁相环的关键部件,压控振荡器(Voltage-ControlledOscillator,VCO)产生锁相环的输出时钟信号,其特性直接决定锁相环性能的好坏。

  9. It has been the core module in analog and mixed-signal circuits and widely used in lots of fields , such as digital circuits and wireless system , communication , etc. Charge-pump phase locked loop ( CPPLL ) is a typical sort of PLLs .

    它已成为当今许多数模混合电路的核心模块,广泛应用在数字电路、无线通讯等领域。

  10. In the end , the phase noise performance of subharmonic sampling phase-locked loop and digital PLL using frequency divider are analyzed and compared . The result shows that the former has more superior phase noise performance if both of the PLLs use the same reference and VCO .

    最后分析和比较了分谐波采样式锁相环和分频式锁相环的相位噪声性能,得出了在相同的参考源和压控振荡器条件下,前者的相位噪声性能更优的结论。