pll
- 网络锁相环;锁相环技术;锁相环控制
![pll](../cache/573552.jpg)
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A System of Measuring Displacement Based on MPU and PLL Technology
基于单片机与锁相环技术的位移测量系统
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This thesis adopt the non PLL method to solve the above problems .
本文采用了无锁相环技术来解决这些问题。
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A new method of characteristic parameters of second order PLL
二阶PLL特性参量的一种新测试方法
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System Level Design and Simulation of a Third Order Charge Pump PLL
三阶电荷泵锁相环系统级设计与仿真验证
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Analysis and Design of RF Signal digital Tuning System Based on a PLL Technology
基于PLL技术的射频信号数字调谐系统的分析设计
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A Phase Frequency Detector without Dead Zone for High Speed PLL
一种用于高速锁相环的零死区鉴频鉴相器
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The Research on PLL Control Circuit for Induction Heating Power Supply Inverter
感应加热电源逆变器锁相环控制电路的研究
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System Design of PLL Based on Behavioral Model Using Verilog-A
基于Verilog-A行为描述模型的PLL系统设计
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A New Method for Improving Accuracy of PLL Jitter Measurement
一种提高锁相环抖动测量精度的方法
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The automatic tuning system in a PLL technique is simply introduced .
文中简单介绍了锁相环自动调谐系统。
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A New Low Power All-Digital PLL Design Based on VHDL
基于VHDL的一种低功耗新型全数字锁相环设计
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Because the system need the higher speed stability , the speed PLL is adopted .
针对系统需要高精度速度稳定性控制的特点,确定采用速度锁相方法进行控制。
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AC Sampling Technology and Its Application Based on PLL and Double A / D
基于锁相环与双A/D的交流采样技术及其应用
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An Analysis of the Loop Performance of the PLL - FM
锁相调频环路性能分析
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Design of PLL Frequency Synthesizer by the Method of Extreme Value Phase Margin
锁相跳频源的极值相位裕量设计法
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Research on Reducing the Phase Noise of PLL Frequency Synthesizer
降低锁相式频率合成器相位噪声方法研究
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The Application of Digital PLL Frequency Synthesizer in Ground Station
数字频率合成技术在地球站中的应用
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On nonlinear capture function and nonlinear tracing function of PLL based on MATLAB
基于MATLAB的PLL非线性捕获和跟踪性能研究
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Design of PLL Frequency Synthesizer for Digital Tuning System
一种数字调频系统专用频率合成芯片的设计
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Electric energy measurement with harmonics based on robust PLL
基于鲁棒锁相环的谐波环境下电能计量方法
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The Research on Indirect Frequency Synthesizer of Low Phase Noise Digit PLL
低相噪数字锁相间接频率合成器的研究
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An Realization for Signal Generator Based on PLL
基于PLL的信号发生器的实现
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CMOS Implementation of a Wideband Low Phase Noise PLL Frequency Synthesizer
宽带低相位噪声锁相环型频率合成器的CMOS实现
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The Selection Criterion of PLL IP Core Based on Jitter
基于相位噪声的锁相环IP核选择判据
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Application of PLL in Synchronous Digital Network over SDH
锁相环在SDH网络中的应用
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Relationship Analysis between PLL Phase Noise and PLL Bandwidth
锁相环相位噪声与环路带宽的关系分析
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Design of Pseudo-noise Code PLL in High Dynamic Condition
高动态环境中伪码锁相环设计
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The Design and Application of Programmable Digital RF PLL Oscillators
数字可编程微波/射频集成锁相源的研制与应用
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Design of Data Acquisition System for Mine-used High-voltage Distribution Device Based on DSP and PLL
基于DSP和锁相环的矿用高压配电装置数据采集系统的设计
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The Charge Pump 's Influence on Phase Noise of Fractional-N PLL
电荷泵对小数分频锁相环相位噪声的影响