hdl
- 网络高密度脂蛋白;高密度脂蛋白胆固醇;硬件描述语言;好胆固醇
noun
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1
- a lipoprotein that transports cholesterol in the blood;composed of a high proportion of protein and relatively little cholesterol;high levels are thought to be associated with decreased risk of coronary heart disease and atherosclerosis
- Synonym: high-density lipoprotein alpha-lipoprotein
数据来源:WordNet
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The increase of hyperuricemia and LDL cholesterol and the decrease of HDL cholesterol are the main characteristics of young men with CAD .
高尿酸血症、低密度脂蛋白胆固醇增高和高密度脂蛋白胆固醇降低是青年冠心病的主要特点;
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While " surprising ," Shai suggested that the lack of effect on HDL might be due to the relatively short duration of the trial .
虽然“令人惊讶”,Shai提出,缺乏对高密度脂蛋白的影响,可能是由于试验持续时间相对较短所致。
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Study on Method for the Determination of Human Plasma HDL Biological Activity
人血高密度脂蛋白生物活性测定方法的研究
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High Level Design Environment for Digital Integrated Circuit Based on Verilog HDL
基于VerilogHDL的数字集成电路高层设计环境
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Analysis of several problems in digital circuit design by verilog HDL
用Veriloghdl设计数字电路过程中的两个问题
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Method and Its Implementation of Extraction Decision Diagram from HDL Description
HDL描述中决策图模型的提取方法和实现
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A Verilog HDL - based Pipelining Design Method and its Application
基于Veriloghdl的流水线的设计方法及应用
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Two Special Data Types in Verilog HDL and Evaluation of the Variables
Veriloghdl语言中的特殊数据类型及其赋值
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The Design Example of Verilog HDL and Its Simulation & Synthesis
Veriloghdl设计实例及其仿真与综合
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The Basic Methods of FPGA design using Verilog HDL
用Veriloghdl进行FPGA设计的一些基本方法
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The study on enhancing synthetic quality of HDL
提高HDL综合质量的探讨
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Interference of vitamin C on detection of HDL - C and its mechanism
维生素C对高密度脂蛋白胆固醇测定的干扰及其机制研究
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The Verilog HDL has been used in the paper to describe whole algorithm .
在设计中本文使用了Verilog语言对整个个算法进行了描述。
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Design of digital circuit based on Verilog HDL
Veriloghdl数字电路的设计
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Study on the Content of Serum HDL Subclasses in Obese Subjects
肥胖者血清高密度脂蛋白亚类组成的研究
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Its effects in reducing cholesterol and increasing HDL are not apparent .
而未见其具有降低胆固醇及升高高密度脂蛋白的作用。
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The design of this chip sticks to the general methodology of HDL design .
该芯片的设计遵循HDL设计方法学的一般方法。
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Solution for Multiple Driver Problems in HDL
HDL设计中多驱动源问题的一种解决方法
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Enzyme-Link Method for Measuring HDL Receptor on Human Arterial Smooth Muscle Cells
人动脉平滑肌细胞HDL受体酶联测定法
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Application of TCL Script in the Synthesis to HDL Code
在HDL代码设计综合中TCL脚本的应用
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Numeric Circuit and Logic Design Experiments by HDL & PLD
基于HDL与PLD的数字电路与逻辑设计实验
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Design of Multifunctional Digital Clock Based on Verilog HDL
基于Veriloghdl设计的多功能数字钟
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Research fingerprint recognition algorithm IP core in Verilog HDL ( hardware description language ) .
研究基于Veriloghdl(硬件描述语言)的指纹识别算法IP核。
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Effects of HDL Preconditioning on Ischemia-reperfusion Lung Injury in Rat
高密度脂蛋白对缺血再灌注损伤肺组织影响
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Several recent studies also suggest HDL protects arteries by promoting cell healing and repair .
一些最近的研究也表明HDL可通过促进细胞的痊愈和修复而保护动脉。
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Verilog HDL : A Descriptive Language for Hardware in EDA Technology
EDA技术中的硬件描述语言&Veriloghdl
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Variable step optimization method is realized by Verilog HDL , and conducted a functional simulation .
采用Veriloghdl实现变步长寻优法,并对此进行功能仿真。
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At the same time verilog HDL simulation results of the main modules are presented in this thesis .
同时给出了主要模块的Veriloghdl的仿真结果。
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The Verilog HDL which is understood easily is adopted for the paper .
系统采用一种软件硬化的设计思路,应用了Veriloghdl硬件语言,该语言较容易理解。
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The entire control timing is realized by Verilog HDL and CPLD .
整个控制时序使用Veriloghdl语言和CPLD进行了实现。