combinational logic circuit

Using Java to Realize the Combinational Logic Circuit Simulation Platform

用Java实现组合逻辑电路仿真平台

Application of First Degree Boolean Difference for Test Generation of Combinational Logic Circuit

一阶布尔差分在组合逻辑电路测试生成中的应用

An Algorithm for Generating the Least Complete Detection Set of Combinational Logic Circuit

一种求解组合逻辑电路最小完全检测集的算法

Application of duality principle in designing of combinational logic circuit

对偶原理在组合逻辑电路设计中的应用

The Application of Data Selector in the Combinational Logic Circuit

数据选择器在组合逻辑电路中的应用

Digital multiplexer and matrix equation in designing combinational logic circuit

采用数据选择器和矩阵方程法设计组合逻辑电路

A Design for Combinational Logic Circuit Using PLA

利用PLA设计时序逻辑电路

The test pattern generation algorithms for combinational logic circuit and the fault types were discussed .

讨论了组合逻辑电路的故障诊断的方法，故障的类型。

A Study of the Implication and the Input of LSI Combinational Logic Circuit

大规模组合逻辑集成电路蕴含与输入的研究

This paper briefly introduces the basic method of transforming data selector into combinational logic circuit of other functions .

简述了用数据选择器转换为其它功能组合逻辑电路的基本方法。

The method of judge and remove in the phenomenon of race and hazard of the combinational logic circuit

组合逻辑电路中的竞争冒险现象的判断和消除

If the combinational logic circuit is only one output , called the single-output combinational logic circuit ;

如果组合逻辑电路只有一个输出，称为单输出组合逻辑电路；

The realization of a combinational logic circuit simulation platform with Applet technology of Java 2 is introduced in this paper .

介绍了以Java2标准中的Applet技术开发组合逻辑电路网络仿真实验平台的原理。

A special testing sequence input is need for measuring maximum dyna - mic current of a combinational logic circuit .

组合逻辑电路的最大动态电流测试应在电路的原始输入端施加一个特定的测试序列才能实现。

The digital part includes closed loop oscillator , frequency divider , combinational logic circuit , non-overlapping clock generation circuit .

数字部分包含环形振荡器、分频器、组合逻辑门、非交叠时钟产生电路。

Multiplexer is a kind of combinational logic circuit , which can be selected an in-put datum among several data and sent it to out-put port .

数据选择器是一种能从多个输入数据中有选择地将一个输入数据送到输出端的组合逻辑电路。

A systematic analysis is made on the phenomenon of competitive hazard in combinational logic circuit , sequential logic circuit and a brief introduction to the ways to eliminate such disturbances .

比较系统地分析了组合逻辑电路和时序逻辑电路的竞争冒险现象，并介绍消除此类干扰的方法。

Fault diagnosis of the control circuit is researched , and some relative diagnosis ways are given for the test of a few fault phenomena of the combinational logic circuit and the sequential circuit .

通过对控制电路系统故障诊断的研究，对组合逻辑电路的多种故障现象以及时序逻辑电路给出了对应的测试与诊断方法，并提出了控制系统对转子中心位置的搜索方法。

N ( 23,12 ) is an asynchronous combinational logic circuit which can be implemented with 12 majestic-logic gates and 77 exclusive-OR gates .

N（23,12）是一个异步的组合逻辑电路，能用12个大数逻辑门和77个异或门电路来实现。

An algorithm for generating the complete test set of each stuck-at-0 ( s-a-0 ) and stuck-at-1 ( s-a-1 ) single fault in a combinational logic circuit is presented .

提出一种算法，用来产生组合逻辑电路中每个总是0和总是1单故障的完全测试集。

In the proposed way for generating full sequences a combinational logic circuit derived by the generated sequence is used to get the feedback signal , which can makes the length of a period of the sequences equal to 2n .

所提出的满序列发生器设计方法则根据不同的发生序列采用相应的组合逻辑产生反馈信号，结果可使序列长度等于2n。

This paper presented and expounded the principle and way of design in combinational logic circuit based on exclusive-OR gate , pointed out the applicability of this way and the superiority in the optimization of logic design and improvement of circuit function in combination with concrete living examples .

提出井阐述了以异或门为基础的组合逻辑电路的设计原理和设计方法，结合具体实例，指明了谊方法的适用范围，以及在优化逻辑设计、提高电路性能方面的优越性。

An improvement algorithm of CAD software of multiple output combinational logic two stage circuit

综合多输出组合逻辑二级电路CAD软件算法的改进二、末日意识