Altera FPGA

Design of the download circuit based on ALTERA FPGA / CPLD

基于ALTERA的FPGA/CPLD下载电路设计

Partly serial FIR filter based on Altera FPGA

基于AlteraFPGA的部分串行FIR滤波器

This paper introduces a way to implement an encryption network card based on PCMCIA interface by the Altera FPGA .

介绍了采用Altera公司的FPGA芯片实现的基于PCMCIA接口的加密网卡。

Software / hardware co-simulation on altera FPGA

基于AlteraFPGA的软硬件协同仿真

Adopt an up-down method for the digital system , using Altera FPGA series and MAX + plus ⅱ software . Here the method of design and implementation are presented .

采用了数字系统的自顶向下的设计方法，选用了AlteraFPGA系列器件和MAX+plusⅡ软件设计平台。

For this reason , BCH decoding algorithm is discussed and two kinds of decoders of BCH ( 31,21 ) code with Altera FPGA are presented .

作者在本文中探讨了BCH码的译码算法，并用AlteraFPGA实现了BCH（31,21）码的两种硬件译码。

When generating an internal ROM in an Altera FPGA , the memory contents can be specified in a Memory Initialization File ( . mif ) .

当在AlteraFPGA中产生一个内部ROM时，记忆体内容能够在记忆体初始化档（.mif）中得到说明。

The embedded tracking system include the Nios processor system , image sample / display model and communication model . The tracking system is implemented at Altera FPGA development kit , and use the Niso processor to complete the tracking algorithm .

跟踪系统包含Nios处理器系统、图像采集和显示模块、外部通信模块等，硬件电路的验证在Altera的FPGA开发板上完成，利用Nios处理器来完成主要的跟踪算法。

In this paper , a new separate adjust variable step-size blind equalization algorithm is proposed for PAM and QAM modulation , and this new algorithm is realized with Altera 's FPGA device .

本文提出一种适用于PAM和QAM调制信号的主副抽头分别调整变步长的盲均衡算法，并使用Altera公司的FPGA器件实现。

In the design implementation and simulation , the Altera Cyclone FPGA device is utilized and the linear interpolation algorithm adopted , then the linear frequency modulation ( LFM ) signal can be easily generated .

利用Altera公司Cyclone系列芯片采用线性插值法进行设计实现与仿真，并且很方便地实现线性调频信号（LFM）的产生；它具有较高的频率分辨率、频率转换速度快以及相位噪声低等优点。

Hardware include Altera series FPGA , the data storage circuit , IC card reader circuit segment liquid crystal display circuit , voltage regulator and the detection circuit , the motor valve drive circuit and the hardware watchdog circuit .

硬件主要包括Altera系列FPGA、数据存储电路、IC卡读写电路、段式液晶显示电路、电源稳压和检测电路、电机阀门驱动电路和硬件看门狗电路。

It introduces the designing process in detail by presenting an instance of realizing a 16 tap FIR filter on Altera 's Cyclone FPGA .

并以一个十六阶低通FIR数字滤波电路在ALTERA公司的CYCLONE系列FPGA芯片上的实现为例说明了设计过程。

The method of the In-System Reconfiguration based on ALTERA CPLD / FPGA is introduced . The download circuit for ALTERA MAX and FLEX is given .

介绍了ALTERACPLD/FPGA可编程逻辑器件在系统配置方法，给出了ALTERAMAX和FLEX系列器件的下载电路。

A multi-mode stepping motor controller was designed by the FPGA instrument . The design process of each functional block of the controller developed by the software Quartus ⅱ 4.1 devoted to the Altera Company 's FPGA development was described . Its feasibility was successfully validated in the FPGA instrument .

应用FPGA器件设计了多模式步进电机控制器，描述了应用Altera公司FPGA编程软件QuartusⅡ4.1设计控制器各功能模块的过程以及调试方法，并成功地在FPGA器件上验证了设计的可行性。

What 's more , CRT display module based on Altera 's large scale FPGA chip is designed and developed as well .

设计并实现了基于ALTERA公司大规模FPGA芯片的CRT显示板；