clock speed

This machine has a clock speed of 1.6GHz .

这台机器的时钟频率为1.6千兆赫。

The first is new " multi-core " processor chips , in which performance is improved not by increasing clock speed , but by building several processing engines , or " cores " , into each chip-a far more energy-efficient approach .

首先是新型“多核”处理器芯片，它在每个芯片中加入若干个处理器引擎或称“内核”来提高性能，而不是靠增加时钟频率。

Besides the clock speed , the technology used in a processor can affect performance .

除时钟速度外，处理器使用的技术也会影响性能。

Each coin will affect the clock speed by 0.4 seconds per day .

一枚便士硬币将导致大本钟每天0.4秒的误差。

There are constraints on the CPU clock speed related to the baud rate .

波特率会对CPU时钟速度产生限制。

I would rather buy920 , and water cool it to achieve maximum clock speed .

我宁愿买920，和水冷却，以达到最大时钟速度。

Intel had decided that the clock speed of its processors should be the standard for performance improvements .

英特尔曾经认为，其处理器的主频应成为性能改善的衡量标准。

When processors operate at a lower clock speed , they consume proportionately less power and generate less heat .

当处理器以较低的时钟速度运行时，它们消耗的电能和产生的热量也相对较少。

This dynamic scaling of the clock speed gives some control in throttling the system to consume less power when not operating at full capacity .

时钟速度的这种缩放可以控制系统在未全力运行时消耗较少电能。

The latency of memory is measured in nanoseconds as it is typically independent o ­ n processor clock speed .

潜伏期的内存是衡量纳秒，因为它通常是独立于处理器的时钟速度。

Operating at clock speed of 50 MHz in FPGA , the multiplier can meet the demand of DTR .

该乘法器在工作频率为50MHz的FPGA芯片中工作正常，可以满足光盘的DTR要求。

Moreover , layout design is also included in this paper and some methods which can be used to improve the clock speed of the micro-processor are discussed , too .

并通过版图设计的考虑，探讨了提高所设计微处理器的时钟速度的方法。

Time is short life ; but even if the target clock speed along with life , to one hour we end to this period of time was also engaged to spend too long .

生命的时间是短促的；但是即使生命随着时钟的指针飞驰，到了一小时就要宣告结束，要卑贱地消磨这段短时间却也嫌太长。

Gallium arsenide switches ten times faster than silicon All of a sudden , I 've got a clock speed ten times faster with no change in design .

砷化镓启动的速度是硅的10倍，突然，我得到了10倍快的时钟速度，但是设计没有发生任何改变。

As the name implies , this governor 's goal is to get the maximum performance out of a system by setting the processor clock speed to the maximum level and leaving it there .

顾名思义，此调控器的目标的通过将处理器时钟速度设置为最大级别而实现最大的系统性能。

Increasing the window size and the issue width to extract more ILP may hinder from achieving high clock speed , limiting over-all performance , especially for the forthcoming billion-transistor per-chip era .

在这种情况下，再增加动态指令窗口的体积和发射宽度将无助于高主频的实现，难以开发更高的ILP，获得整体性能的提升。

Dynamic frequency reconfiguration technology , which allows the clock speed of circuit module to be dynamically changed by software , supports some advantages , such as minimizing power draw and heat dissipation , extending module life , and so on .

时钟频率动态重置技术，是指通过软件动态地改变电路模块的工作时钟频率，以达到降低功耗、减少散热，延长电路模块使用寿命等作用。

The industry and market needs to promote the performance of electronic systems . As the semiconductor technology advances , the on-chip clock speed and board-level clock speed increases yearly . High-speed circuit bandwidth has accessed to the traditional circuit microwave frequency bands .

需求不断地推动着电子学系统的性能发展，随着半导体工艺的进步，片上时钟的速度和板级时钟的速度都在逐年提高，信号的带宽已经进入了传统的微波电路的频带范围。

While its quad-core " Shanghai " Opterons reached a maximum frequency of2.3GHz , the six-core part had to give up some clock speed , down to1.8GHz , to manage the thermal load for six cores .

虽然它的四核心“上海”Opteron处理器达到了2.3GHz的最高频率，六核心部分不得不放弃一些时钟速度，降低到1.8GHz，以管理六核热负荷。

Circuits Design of Hanging Clock and Speed Display for Automobiles

车用悬挂式时钟速度显示电路设计

The three controlling circuits with fast and low clock in code speed adjust technique are designed .

设计了正码速调整技术中快慢时钟的三种控制电路。

The design makes the most of hardware resource Spartan-II chip , and adopts pipeline and parallel mode in order to improve the system clock and decode speed .

为充分利用Spartan-II芯片的硬件资源，编译码器采用了流水线方式与并行方式，并提高了系统时钟频率。

Intel Core i5 and Core i7 operates well below its thermal and electrical limits , allowing the Turbo Boost to " overclock " the CPU clock frequency and speed .

英特尔的Corei5和Corei7运行，远低于其热和电的限制，使涡轮推动的“超频”的CPU时钟频率和速度。

Clock study of high speed interleaving / multiplexing data-acquisition system

高速交替/并行数据采集系统时钟研究

Exploring Source Synchronous Clock Implementations for High Speed Interfaces

针对高速接口的源同步时钟实现方案的研究

The total result keeps the clock at the same speed . The general consequently promised to withdraw his troops speedily from Mexico .

这种变化最终使得钟走的速度正好。将军最终答应将军队快速撤离墨西哥。

doing so won 't turn the clock back at warp speed ( if at all ) , and may even clog your pores or cause other damage .

对于你来说，它不能让时光飞速倒流（即使它真的有效），而且可能堵塞你的毛孔，导致其他伤害。

Unlike CISC processors , RISC engines generally execute each instruction in a single clock cycle , which typically results in faster execution than on a CISC processor with the same clock speed .

不像CISC处理器，一般的RISC引擎执行在一个时钟周期，每个指令，在快上具有相同的时钟速度的CISC处理器执行一般的结果。

In the entire structure , we choose multiphase data extraction technology to sample data . By using four-phase clock ( from CDR ) to sample the serial data , we can sample a high-speed serial data stream at a lower clock speed .

数据采样在整体结构上采用了多重相位数据提取技术，用四个相位的时钟（从CDR恢复出来）来采样串行数据，这样就可以用低的时钟速率采样高速的串行数据流。

After the number of clock cycle has been properly lengthened and the operations during the cycle simplified , the 1D DCT / IDCT can be executed within 8 clock cycles at high speed .

通过合理安排时钟周期数和简化各周期内的操作，使1DDCT/IDCT模块能在八个时钟周期内快速完成一次变换。