Memory latency

Given these trends , it was expected that memory latency would become an overwhelming bottleneck in computer performance .

鉴于这些趋势，预计内存延迟将成为压倒性的计算机性能的瓶颈。

Today , chip-level multiprocessing provides more CPUs on a single chip , permitting even greater performance due to reduced memory latency .

现在，芯片级多处理能够在单个芯片上提供更多的CPU，由于减少了内存延迟，因而可获得更高的性能。

Software data prefetching is an effective technique for hiding memory latency .

软件数据预取是一种有效的隐藏存储延迟的技术。

To hide memory latency , NPs employ large register file for large number of registers .

为了隐藏访存延迟，网络处理器往往采用较大的寄存器文件，增加寄存器的数量。

Thus , it is important to study protocols and implementation of system bus to hide memory latency and increase memory access rate .

因此研究系统总线协议及其实现技术对于隐藏访存延迟和提高访存速度具有重要意义。

Off-chip memory latency is mainly determined by DRAM latency , and memory bandwidth is determined by data transfer rate through the memory bus .

片外存储系统的访存延迟主要由DRAM延迟决定，带宽则是由内存总线的数据传输率所决定。

It provides several effective methods of load balancing and reducing shared memory access latency .

主要介绍了几种有效的负载均衡策略和减少共享存储访问延迟的优化手段。

Hiding Memory Access Latency in Software Pipelining Storing Methods of Chinese Font in LCD

软件流水中隐藏存储延迟的方法液晶显示器汉字字模存储方法

As processor gets much higher speed , the memory access latency becomes a bottleneck that restricts higher performance .

随着处理机运行速度的逐渐提高，存储访问延迟成为性能提高的瓶颈。

By using data live range extension technique , the parallelism is exploited to hide the memory access latency .

通过数据生存期扩展技术，还能有效地进行计算与访存并行的开发，从而隐藏存储访问延迟。

The program could hide memory access latency well when it has high compute density ( the ratio of computing time to memory access time ) .

当对于并行数据集有较高的计算密度（即计算时间和访存时间的比率）时，能够很好的隐藏存储器的访问延迟，不需要很大的数据缓存。

To solve this problem and reduce memory access latency , memory hierarchies in the form of one or more levels of cache have been used extensively in current computer systems .

为了解决存储墙问题，减少存储访问延迟，当前的计算机大都采用层次存储系统。

By adding buffers , we implemented the pipelining of EDMA reads / writes which enhances the parallel processing ability and hides the memory access latency .

通过增加使用缓冲器实现了EDMA读／写操作的流水化，提高了并行处理能力，隐藏了存储器的访问延迟。

Test for memory : Latency and times of errors in step down test in the injection group were better than those in the control group , and differences were significant ( P < 0.01 or 0.05 ) .

记忆实验：自制银杏黄酮注射液组与德国产银杏黄酮注射液组跳台实验潜伏期和5min错误次数均明显好于对照组，差异具有显著性意义（P<0.01/0.05）。

This thesis analyzed key technologies of GMS ; including service mode and programming model , scalable architecture design , interconnect protocol and network , intelligent memory management and latency tolerance .

针对GMS模型的特点，提出并分析了需要重点解决的关键技术问题，包括访问接口与编程模型、可扩展的架构和互连协议、智能内存和延迟隐藏等。

All modern CPUs must utilize local memory cache to minimize latency of fetching instructions and data from memory .

所有现代的CPU必须使用本地存储的缓存，将获取指令和数据的延迟降到最低。

We design a scheduling strategy , called Golden Mean ( GM ), to balance between the memory usage minimization and latency minimization by taking the situation of the future workload , the current memory consumption and QoS requirement of the query into account .

我们设计的GM调度策略综合考虑了将来的负载变化、当前的内存消耗状况以及用户对于主要性能指标的偏好与要求，在系统内存最小化和结果输出延迟方面取得平衡。

Of the learning and memory abilities , the latency period was obviously shortened in the treatment group . With mid-and low-dose of EFSP the movements in 20 % of marginal zone were decreased and the movements in 80 % of center zone were increased .

学习记忆方面，四逆散有效部位治疗组潜伏期显著缩短，中小剂量组20%边缘区域运动明显缩短，80%中心区域运动增加。

The tightly-coupled nature of the CMP allows very short physical distances between processors and memory and , therefore , minimal memory access latency and higher performance .

CMP紧密耦合的本质使处理器与内存之间的物理距离很短，因此可提供最小的内存访问延迟和更高的性能。

In modern high performance architecture , to balance the computation and memory access , optimize the memory bandwidth and latency , software-managed memory hierarchy is increasingly used instead of hardware-managed cache hierarchy .

现代的高性能计算机体系结构中，为了更有效地实现计算与访存的平衡，优化访存带宽和延迟，越来越多地采用软件管理的多级存储层次来替代硬件管理的多级cache存储层次。

Software pipelining has been combined with several memory optimization technologies for higher performance by hiding memory access latency .

为了减轻存储系统影响，软件流水结合了一些存储优化技术，通过隐藏存储延迟来提高性能。

Event-related potential P300 as a certain extent can reflect hominine function of memory , especially the amplitude of the P300 can reflect the updating of token in the working memory and the latency of the P300 deputy the time which estimate and classify the excitant .

事件相关电位P300在一定程度上可以反映人的记忆功能，特别是P300的波幅反映工作记忆中表征的更新，其潜伏期代表对刺激物评价和分类所需要的时间。

Based on the analysis of memory access features of block execution model in TPA-PI , we propose the second optimization to L1 data Cache in TPA-PI , reducing memory access latency by making use of data prefetch mechanism .

分析了TPA-PI块执行模型的访存特征的基础上，提出了对TPA-PI的一级数据缓存设计的第二种优化&利用数据预取机制降低访存延迟。